I monitored the gate voltages of all the fets both in real circuit and simulation and no problem, the gate driver can supply up to 200V already.
I think the images uploaded are not clear?! so let me explain some.
this is not an audio amplifier.I will use it in a underwater sonar application. the bandwidth is between 10-85khz. I use pwm as a modulator. pwm frequency will be about 800khz (if I can solve the heating problems). my supply voltage will be about 55V and I use full bridge output.
I use a filter (below) which has cut-off frequency:100khz
---------10uH------------------5uH------------------------
f - - -
u - - -
l - - -
l 247nF 47nF 8ohm
- - -
b - - -
r - - -
i - - -
d - - -
---------10uH------------------5uH------------------------
*my problem is when I connect a resistor as a load to the full bridge output the fets is not so hot (at about 45C degree) but when I connect an inductive load like above its temperature continuously increase.
I simulated the circuit in ltspice and at some switching times there is large current spikes through high and low side fets.. and I couldnt actually why is this happening. after that I looked at the real circuit if there are lare spikes like in simulation but NO, there wasn't.
I'm having trouble with attachments.. I'll upload the schematic and required files when it is solved
Do You see these spikes both with Resistive and Inductive load while modelling?
And do they disappear in real-life cirquit with both type of load either?
I see spikes only in simulation with inductive loads...
yes in real life circuit there is no spike in with both loads.(inductive or resistive)
yes in real life circuit there is no spike in with both loads.(inductive or resistive)
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Drawings, like schematics, PCB layout, etc. can be packed very effectively by lossless methods. PNG, GIF, TIFF. JPEG should be avoided, because it's lossy.
Repeating already known info is not neccessary. But there are unknown things. Some of them I explicitely asked, some of them I just mentioned.
Repeating already known info is not neccessary. But there are unknown things. Some of them I explicitely asked, some of them I just mentioned.
Volkantr,
can You provide Real-life circuit oscillogram of Gate voltage of upper and lower transistors (syncronously) for both resistive and inductive loads?
hi,
Finally I'm able to upload files again. I measured the gate voltages and current through the fets for two conditions. no load and with an 8ohm resistor(resistor by winding and I think it has some parasitics.)
I uploaded the schematic and images. I hope it helps to make things clear.
and with no load condition, I think there is shoot through but I want to hear your comments.. thanks again.
Btw: I'm not using the transducer for now but if you want I can model and upload it..
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Nice!
Who is Blue, Red, Green and Yellow in oscillograms?
Where did You inserted Your 0,47 Ohm resistor?
Would be great!
P.S.: Ah, and Real-Load (w/transduser) oscillograms would be interesting to see.
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blue: right-high side-Fet
yellow: right-low side -fet
pink:left-low side-fet
green:left-high side-fet
I upload a new schematic that show the 0.47ohm sense resistor in red circle.
as soon as I got the transducer I'll take the gate voltage measurements
by the way another important parameter. with no load condition! I see nearly 90mA (RMS) flows through the FETs. and also FETS are getting hot again.
I think that means the is cross conduction. I will try slowering high side fets and removing the back-diodes to see if there is any healing..
I'm waiting ur comments..
thanks.
Obviously, Your right-side malfunctions (only the last oscillogram left some doubts): Yellow & Blue do not have their "dead-time".
Are You sure Your right and left parts are 100% identical?
Are You sure Your right and left parts are 100% identical?
Denniz!
They have. Be careful! High side gate voltage is superpositioned on output voltage!
Volcantr!
Now only 2 or 3 more measurements and some other datas (modulating signal waveform, idle state measurements, etc...) are needed to really start debugging! Filter schematic in understandable form also.
They have. Be careful! High side gate voltage is superpositioned on output voltage!
Volcantr!
Now only 2 or 3 more measurements and some other datas (modulating signal waveform, idle state measurements, etc...) are needed to really start debugging! Filter schematic in understandable form also.
I compiled all the images together and I simplified the schematic. I named the important nets on schmatic(pdf) file and I got the measurements and named the measurements with the same name in the schematic file.
the only signal I couldnt measure is "right" (as in the schematic file) because the board was so crowded that I couldnt solder the probe and I gave up.
as you see in the schematic file I measured all the signals with no load. because the FETs heating without the loads already. and I thought the problem is not about the loads but if anybody desires I can take measurements with load...
I hope it is clear and enough..
thanx
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I don't really understand why to measure (only) without load. Loss components are different without load. And you won't use it this way.
What is more interesting: operation with load, but without modulation signal. (Duty cycle=50%.) You may will be surprised!
The previous waveforms were perfectly normal (except for the current, which is unexplainable). There is a small sign of turning on again at switched off gates. This is usual, but can cause cross conduction! Harder gate pull down, or increased Cgs may help!
What is more interesting: operation with load, but without modulation signal. (Duty cycle=50%.) You may will be surprised!
The previous waveforms were perfectly normal (except for the current, which is unexplainable). There is a small sign of turning on again at switched off gates. This is usual, but can cause cross conduction! Harder gate pull down, or increased Cgs may help!
-sorry I couldn't understand. what do you mean by harder gate pull down? do you mean increasing resistor between gate and source?
-increased Cgs adding capacitance? and are those usual ways to prevent the said problem? I'm really a trainee..
In TEK0041 etc I assume you're using a x10 probe, in which case the gate drives would be about 4.6v on the low side and 27v on the high side. Am I right or have I misinterpreted your oscillograms?
The schematic seems to indicate a power Vdd of 50v, and a driver Vdd of 12v. Is that correct?
Just trying to be sure I understand the conditions here, before commenting, maybe incorrectly.
The schematic seems to indicate a power Vdd of 50v, and a driver Vdd of 12v. Is that correct?
Just trying to be sure I understand the conditions here, before commenting, maybe incorrectly.
assume probe x25. I posted the description of the home made probe in the before attachments. I could not upload it again cuz I'm on a different machine now (that uses macos as O.S) and it gives error when uploading file.
PNP pull down, or UCC27200 gate driver (for example).
Not really usual, it's a compromise in emergency.
1050/50=21
But what is the current/div?
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