Transformers from conventional computer PSUs are designed for proportional BASE drive of bipolar transistors and are *abstolutely* not suitable to drive MOSFET gates. They may be rewound into gate drive transformers, though.
Hi, Eva
Sorry for late reply(school).
That gate trafo is toroid, witch i got it from my local dealer (Iskra)
I have just wound 20 turns for every side.They were not in layers.
The results were expacted.
Now I have in my posession IR2110 from Farnell. Mean while I have salvage some old PC supply,made it to work, then put my own trafo in.It is working on mains voltage@120w working as it should. Now I will try to get the same or better🙂 results with IR.
Sorry for late reply(school).
That gate trafo is toroid, witch i got it from my local dealer (Iskra)
I have just wound 20 turns for every side.They were not in layers.
The results were expacted.
Now I have in my posession IR2110 from Farnell. Mean while I have salvage some old PC supply,made it to work, then put my own trafo in.It is working on mains voltage@120w working as it should. Now I will try to get the same or better🙂 results with IR.
Attachments
luka said:
That gate trafo is toroid, witch i got it from my local dealer (Iskra)
I have just wound 20 turns for every side.They were not in layers.
The results were expacted.
A example how to NOT wound gate drive transformer... your construction will maximize leakage inductance, baad. very baad.
Try bifilar winding of primary/secondary, maybe primary and secondary wire twisted together before winding.
GTD transformers should look something like these(with shorter wires if possible) http://www.ee.oulu.fi/~masaj/class-d/P1040022.JPG
This transformer layout will give very poor gate drive performance because non-overlapped windings yield high leakage inductance. Transformers wound in that way may only provide reliable gate drive when suitable gate buffers with high input impedance are employed.
You should overlap the three windings and spread them evenly across the circumference of the toroid, as this will produce the best performance. Leaving the primary and secondary magnet wires in direct contact is right as long as the control circuit is also in the primary side (thus no critical isolation is required) and you put great care in not crossing, stretching or scratching the wires.
If the control circuit is in the secondary side, you should isolate the primary from the secondaries with three layers of mylar tape (quite messy to apply in a toroid). You may also consider a pair of smal EE20 cores and a suitable coil former, as proper winding insulation is much easier to achieve with these. Another alternative is winding the primary of the toroid with triple-insulated wire.
I also have some IR2112 (same as IR2110 but with lower current rating), but I like transformers because they allow to deliver both power and signal to each gate drive cell as an easy way to implement secondary-side control, and because they feature superior dV/dt false-trigger inmunity in comparison with floating ICs and optocoupler based drive systems. Their only drawback is that they are only mainly suitable for high frequencies and "symmetrical" switching.
EDIT: I have tried twisted bifilar and trifilar winding against paralell evenly-spread 1:1 or 1:1:1 winding and I was not able to measure any difference other than increased capacitances and more ringing. It didn't improve rise and fall times at all.
You should overlap the three windings and spread them evenly across the circumference of the toroid, as this will produce the best performance. Leaving the primary and secondary magnet wires in direct contact is right as long as the control circuit is also in the primary side (thus no critical isolation is required) and you put great care in not crossing, stretching or scratching the wires.
If the control circuit is in the secondary side, you should isolate the primary from the secondaries with three layers of mylar tape (quite messy to apply in a toroid). You may also consider a pair of smal EE20 cores and a suitable coil former, as proper winding insulation is much easier to achieve with these. Another alternative is winding the primary of the toroid with triple-insulated wire.
I also have some IR2112 (same as IR2110 but with lower current rating), but I like transformers because they allow to deliver both power and signal to each gate drive cell as an easy way to implement secondary-side control, and because they feature superior dV/dt false-trigger inmunity in comparison with floating ICs and optocoupler based drive systems. Their only drawback is that they are only mainly suitable for high frequencies and "symmetrical" switching.
EDIT: I have tried twisted bifilar and trifilar winding against paralell evenly-spread 1:1 or 1:1:1 winding and I was not able to measure any difference other than increased capacitances and more ringing. It didn't improve rise and fall times at all.
Smps
P1 is Sec without any load
P2 is volta across whole Pri
and the movie is the point betwean the mosfets [2v/div]
we have big problems with constructing trafo in the right way.Each trafo is made of 2x14 on pri and 3x11 on sec.They (pri) are conncected in series.Core are ETD34.
http://freeweb.siol.net/alecnik1/P1.jpg
http://freeweb.siol.net/alecnik1/P2.jpg
http://freeweb.siol.net/alecnik1/M.MOV
Lep pozdrav, Luka
P1 is Sec without any load
P2 is volta across whole Pri
and the movie is the point betwean the mosfets [2v/div]
we have big problems with constructing trafo in the right way.Each trafo is made of 2x14 on pri and 3x11 on sec.They (pri) are conncected in series.Core are ETD34.
http://freeweb.siol.net/alecnik1/P1.jpg
http://freeweb.siol.net/alecnik1/P2.jpg
http://freeweb.siol.net/alecnik1/M.MOV
Lep pozdrav, Luka
I'm sorry to say that but these waveforms look really ugly, and the video really scared me because these traces look exactly as if something was going to explode right now
I feel a strong reflex to disconnect power when I see such things.
There is something really wrong in your transformers or your circuit. Waveforms should look perfectly square. Also, why are you employing such a big core (ETD34) and connecting the magnet wires in series? I don't fully understand your series connection.

There is something really wrong in your transformers or your circuit. Waveforms should look perfectly square. Also, why are you employing such a big core (ETD34) and connecting the magnet wires in series? I don't fully understand your series connection.
I intend to have 2 trafos etd34 because of small hight.
I will post soon pic , how do i have evertying connected.
For driver i use Ir2110, witch I belive is the problem (high side mosfet)
I will post soon pic , how do i have evertying connected.
For driver i use Ir2110, witch I belive is the problem (high side mosfet)
Coupling
Luka,
Did you re-wind your driver transformer to couple the windings, like EVA and others suggested? This is crucial, as it will minimize leakage inductance. The pic you posted of your driver transformer shows a winding technique that MAXIMIZES leakage inductance like EVA and everyone else mentions. I would seriously re-wind this before doing anything else, keeping in mind high-voltage protocols.
Steve
Luka,
Did you re-wind your driver transformer to couple the windings, like EVA and others suggested? This is crucial, as it will minimize leakage inductance. The pic you posted of your driver transformer shows a winding technique that MAXIMIZES leakage inductance like EVA and everyone else mentions. I would seriously re-wind this before doing anything else, keeping in mind high-voltage protocols.
Steve
I use ETD34 with material 35G
http://freeweb.siol.net/alecnik1/ETD.pdf
I belive C4 is the main problem,because the mid point between the fets is not falling on 0V,so the C4 is not chareged to 12V,but to 4v or less.But this can't be the only problem,because the sec is producing strange waveform even with no load connected.Can you dirrect me to
some applicatin note of some company, how to build trafo properly (in PDF).
http://freeweb.siol.net/alecnik1/smps.jpg
http://freeweb.siol.net/alecnik1/ETD.pdf
I belive C4 is the main problem,because the mid point between the fets is not falling on 0V,so the C4 is not chareged to 12V,but to 4v or less.But this can't be the only problem,because the sec is producing strange waveform even with no load connected.Can you dirrect me to
some applicatin note of some company, how to build trafo properly (in PDF).
http://freeweb.siol.net/alecnik1/smps.jpg
I have tried to connect only one trafo and in diffrent way and this is what I get:
output 10v/div, load 12 ohm
http://freeweb.siol.net/alecnik1/P11a.jpg
output 10v/div with no load
http://freeweb.siol.net/alecnik1/P12a.jpg
output 10v/div, load 12 ohm
http://freeweb.siol.net/alecnik1/P11a.jpg
output 10v/div with no load
http://freeweb.siol.net/alecnik1/P12a.jpg
In your schematic, the VS pin of the IR2110 is not connected to the source of the high side MOSFET.
> push pull with two mosfets 500V in series?
Do you mean using two each in series (per leg) to reach the 1000V spec? Forget it. Quickly. Please!
Do you mean using two each in series (per leg) to reach the 1000V spec? Forget it. Quickly. Please!
Do you mean using two each in series (per leg) to reach the 1000V spec? Forget it. Quickly. Please!
WHY?
why it would not be possible?
Are there any mosfets like irfp460 but that can handle 800-1000V but LOW resistance too ?
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