It's my favorite
It shines and sonically outperforms all the logic inverters being used in the Well Tempered Master Clock thread.
I just wish they also made a cml output
The thing that keeps popping out is how to get from a sine signal (crystal) to really fast edges?
Since every squaring step also amplifies and generates phase noise.
What's the minimal (lowest) edge rate that's needed to ensure best phase noise and jitter specs?
Many phase noise measurements can measure sine waves, yet no one uses those to clock the parts.
The part that's missing is the edge needed to reach best measurement results, this depends on used dac structure, pcb layout and family used, probably more things. Once you've chosen a logic family the edge rates needed are by that fixed.
Realy cool, quick'n dirty implementation Marcel
The interleaved dac structure is used in Tektronix' AWG's, see attached picture.
Link:
https://www.google.com/url?sa=t&sou...FjAIegQIBRAB&usg=AOvVaw39N4uCW5WZswm6aDcYkkv-
Looking at the picture it uses different physical dacs,1 for odd and 1 for even parts of the datastream. It seems the even order dac never spits out every other bit, demultiplexed.
Looking closer to the problems they faced, they may only be of interest for the extra bandwith they achieve by effectively doubling the bandwith, but I think it concerns all data.
I took your solution as resembling this structure, with the tight matching it needs.
Who said it needs tight matching? It needs some degree of matching, that is, the even and odd weights should not be totally different.
Anyway, there is some similarity, but the Tektronix scheme converts different data with the odd and even DACs, while the scheme I wrote about converts the same data with the odd and even DACs (at half a clock cycle shifted moments).
OSR has nothing to do with modulation depth. Modulation depth(amplitude usage) depends on the order of 1bitDSM. The lower the 1bitDSM order, the more modulation depth. ADC and DAC also have the same restriction, where ADC is from analog to 1bitDSM pulse train, and DAC is from 32bit or 24bit PCM to 1bitDSM. If you use multibit DSM, more than 5bit has almost no restriction. 2bit, 3bit, and 4bit have some restrictions.
Rough output pulse train in 1bitDSM in 16 successive bits.
11111111 11111111 the 1st order and 2nd can output 16 ones;100%.
11111110 11111110 the 3rd can do 14 ones and 2 zeros;75%.
11111011 11011110 the 4th is 13 ones and 3 zeros;63%.
11101110 11101110 more than 6th are 12 ones and 4 zeros;50%.
I don't think SACD can output 24 ones and 4 zeros because it employs 7th order DSM. "Zero" of SACD is 11010010, which means 4 ones and 4 zeros. You can't choose both 11110000 and 11100010 because more than 3 successive ones or zeros mean low frequency. High order DSM doesn't allow to have low frequency, where the noise-shaping algorithm wipes away low frequency.
OSR in DSM and sampling frequency in PCM have the same meaning. As long as your bandwidth is satisfied, high OSR and high sampling frequency are redundant. If your BW is 20kHz, 64OSR with more than 7th order is enough. If 128OSR, more than 4th is enough. The difference is out of band noise like PCM.
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I think that's a too static way of looking at it.
Because how else would you control pre or post ringing (filter slopes) if it's just a random pulse train where you can take an arbitrary row of bits out of the stream and define 0 as an even sum of 1's and 0's? The exact sequence of these 0's and 1's must have specific meaning. In other words: how can you control Filter types as well as Algorithms within a specific OSR and have volume control if all modulation depth is fixed by choice of an order?
I can't see this being a fixed thing within pcm to dsm conversion.
A sacd pressing plant will discard a master if it doesn't follow this 24/28 rule (4/28).
All I'm saying is that higher OSR might relax modulation depth rules. Or there is another explanation to why high levels of modulation depth generate lower distortion at higher OSR, or HQPlayer uses some secret ingredient (internediate stage with multi bit DSM perhaps?).
Human hearing NOT based on frequency... Its based on time!
With all due respect you are wrong, so wrong that it is painful to read as you are clearly a highly educated and intelligent engineer and this one falsehood is blinding you other possibilities.
This is the single most damaging falsehood accepted as irrefutable fact by 99.99% of all audio designers, electronic / digital and mechanical / transducers.
Highly abbreviated explanation of my statement:
(1) Ignoring bone conduction and sub 20Hz infrasound, 100% of human hearing is based on air pressure changes. Nothing else, frequency variation does not feature in the detection of sound, only later in the brain decoding of sound does frequency variation come into play.
(2) In a vacuum we cant hear anything because there is no air to increase / decrease (compression / rarefaction) in pressure.
(3) These Air Pressure Events (APE's) have a clearly defined start time, duration and end time and it is this timing information which forms 100% of the sound input information which is sent to our brain.
(4) ALL spatial / 3 D sound information is decoded using time domain data... NOT frequency domain!! Please consider the implications of this fact.... The number crunching power required in order to accurately process the tiny (low digit micro not milli second) differences in arrival time from left to right ear as an insect flies around our head while we monitor dozens of other jungle sounds are way beyond any computer and is at the heart of our "fight or flight" response.
(5) Our eardrum(s) moves due to these APE's and then the tiny hairs / nerve ending / inner ear biology and brain combine to perform the most astonishingly accurate decoding, identification and location of all sounds.
Deep understanding of just how remarkable our ear brain combination is only just shedding light on this complex subject and audiology is an exciting area of discovery which is now "cool" again thanks to the recent popularity of 3D audio ie Dolby Atmos / VR and gaming which demands the most accurate location of sounds in 3D space in order to identifly the precise location of enemies / prey / teammates etc.
Anyway, sorry to go off topic on an old post, but my point is that human hearing is all about the TIME domain NOT the frequency domain and all audio designers need to understand this fact and incorporate it into their designs... Ironically, IF we had the perfect time domain accurate digital source / DSP processing then the DSP could correct any frequency domain errors and give us the "perfect" frequency response from any loudspeaker, assuming the transducer was able to maintain perfect time domain... HIGHLY unlikely!
Cheers
Alex.
With all due respect you are wrong, so wrong that it is painful to read as you are clearly a highly educated and intelligent engineer and this one falsehood is blinding you other possibilities.
This is the single most damaging falsehood accepted as irrefutable fact by 99.99% of all audio designers, electronic / digital and mechanical / transducers.
Highly abbreviated explanation of my statement:
(1) Ignoring bone conduction and sub 20Hz infrasound, 100% of human hearing is based on air pressure changes. Nothing else, frequency variation does not feature in the detection of sound, only later in the brain decoding of sound does frequency variation come into play.
(2) In a vacuum we cant hear anything because there is no air to increase / decrease (compression / rarefaction) in pressure.
(3) These Air Pressure Events (APE's) have a clearly defined start time, duration and end time and it is this timing information which forms 100% of the sound input information which is sent to our brain.
(4) ALL spatial / 3 D sound information is decoded using time domain data... NOT frequency domain!! Please consider the implications of this fact.... The number crunching power required in order to accurately process the tiny (low digit micro not milli second) differences in arrival time from left to right ear as an insect flies around our head while we monitor dozens of other jungle sounds are way beyond any computer and is at the heart of our "fight or flight" response.
(5) Our eardrum(s) moves due to these APE's and then the tiny hairs / nerve ending / inner ear biology and brain combine to perform the most astonishingly accurate decoding, identification and location of all sounds.
Deep understanding of just how remarkable our ear brain combination is only just shedding light on this complex subject and audiology is an exciting area of discovery which is now "cool" again thanks to the recent popularity of 3D audio ie Dolby Atmos / VR and gaming which demands the most accurate location of sounds in 3D space in order to identifly the precise location of enemies / prey / teammates etc.
Anyway, sorry to go off topic on an old post, but my point is that human hearing is all about the TIME domain NOT the frequency domain and all audio designers need to understand this fact and incorporate it into their designs... Ironically, IF we had the perfect time domain accurate digital source / DSP processing then the DSP could correct any frequency domain errors and give us the "perfect" frequency response from any loudspeaker, assuming the transducer was able to maintain perfect time domain... HIGHLY unlikely!
Cheers
Alex.
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I am asking because I wonder if I can use this topology for "switching" the R2R for instance 24bit discrete dac? I am aware that is different topic, but You already have experience with this BJT topology. Somehow I think that this BJTs will be better sounding than mosfets inside chips usually used for driving and switching R2R net.
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Yes the resistors should be matched and from very small tolerance. For R-2R ladder output DACs.
Yes we're talking about different structures, very similar though.
The interleaving dac should be very well matched. Otherwise every odd or even bit has different energy, as 1 dac never complements (weighs) the other with it's difference in bit length, amplitude etc.
I understand now that your example doesn't use different dacs for every bit (or sum of odd&even bits) in the bitstream, though you could. The part about specifically weighing taps 1 and 2 etc threw me off course, but it's just a standard shift register function , where the zero's are also added. I thought I recognized the interleaved structure;-)
The aim is to achieve an effective doubling of samplerate, while they actually don't no.
The interleaved dac, when well implemented, leaves more usable bandwidth because the noise products of both cancel each other out. So while at high frequencies there's nornally too much noise to be usefull to generate signals, interleaving clears up the noise, generating more available bandwith, effectively doubling the samplerate. Funny thing, right?!
Edit: but I don't see an easy use case for high resolution audio with this.
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Someone please
give a tip for good flip-flop for making shift register. To adopt serial to parallel datas for discrete dac?
I solder one piece with 4 x 74HC164 8bit ShReg. Working fine, but I think that it could be much better with flip-flops. And that will give +data and -data parallel steams. If FF is Q and -Q outputs?
give a tip for good flip-flop for making shift register. To adopt serial to parallel datas for discrete dac?
I solder one piece with 4 x 74HC164 8bit ShReg. Working fine, but I think that it could be much better with flip-flops. And that will give +data and -data parallel steams. If FF is Q and -Q outputs?
The technique described in the Tektronix application note was also used in the early days of cd. It was not about noise but speed and settling time.
Yes, I agree with you that static analysis can't make sense. But you need at least one-second pulse train to have accurate analysis. One second in 64OSR means 3072000 counts; it's impossible to use such number. My rough calculation is averaged one to explain the limitation of modulation depth. You can find successive 8 ones or zeros even in 8th order DSM pulse train, but it occurs two or three times per 1 second. The averaged occurrence of successive one or zero is under control of the order: the higher, the smaller.
High order DSM has many integrators; the 8th has eight. Many integrators easily can change the state of the 1bit quantizer inside the DSM feedback loop because integrator is a kind of accumulator. That's the reason high order has a high-frequency spectrum. In other words, high order DSM can have effective noise-shaping. If you employ high order DSM(many integrators), noise-shaping is an automatic function. 8th order in 64OSR can have 30kHz bandwidth, where you have low distortion up to 30kHz. If 8th order in 128OSR, the BW is 60kHz. 256OSR is 120kHz. You can't control the principle. The only thing is the order.
As long as you are in the digital domain, the principle is true. But our goal is DA conversion, which means the output is always in the analog domain. DAC topology often results in different phenomena in the analog domain. High OSR can sometimes have low distortion and vice versa. There is no concrete principle in the analog domain because DAC topology dominates the situation.
The time domain and frequency domain don't conflict with each other. They are the position where your eyes exist. Some analysis is easier from the time domain than the frequency domain and vice versa. If you want to pass through a maze, you have two choices: from the goal or the entrance. From the goal is an optimum selection. I have many experiences to rip vinyl for my music library. The best noise and click reduction processing system(RX7 by iZotope) for me is frequency domain software. It can do a perfect job to refresh the old school music file. AFAIK, recent excellent mastering software is the frequency domain(FFT based one). You can do the same job in the time domain if you are sure of your success. But It's not easy to improve sound quality if you are in the time domain like the solution of a maze from the entrance.
The accurate phase relation between the 24bit ladder switch can have less glitch impulse than standard mosfet switch. But the performance of multibit DAC depends on resistor accuracy, though less glitch is useful.
Can someone explain how this works? As far as I can make out, splitting the signal stream into odd & even samples, directing them to different DACs with the DAC handling the even samples being slipped by a half clock? I'm probably thick but hat I don't understand is this statement from the Tektronix PDF:
In most DACs bits are processed on the rising edge of the clock pulse so I can't work out how the above two statements make sense?
What am I missing?
As far as I have understood, the Tek architecture requires an adder instead of an analog switch to interleave two DACs because their application is a very high sampling rate. If your fs is 48kHz and the input is 10kHz, The 1st image(odd) is 0-10kHz and 0+10kHz: the target one. The 2nd(even) is 48kHz-10kHz and 48kHz+10kHz. The 3rd(odd) is 96kHz-10kHz and 96kHz+10kHz. The 1st image is used to feed DAC. More than 2nd is images to be removed. That's why your available bandwidth is usually up to 24kHz: fs/2.
In the Tek interleaving system, the two DACs have the same phase images with odd ones but opposite phase with even ones. So, simple addition results in odd images only. The 2nd image(38kHz and 58kHz) will disappear. In other words, the output of the adder is the same data as 2xfs sampling. The two 48kHz sampled DAC can act as one 96kHz sampled DAC by an adder, not switch. If your sampling frequency is very high, It's advantageous.
In the Tek interleaving system, the two DACs have the same phase images with odd ones but opposite phase with even ones. So, simple addition results in odd images only. The 2nd image(38kHz and 58kHz) will disappear. In other words, the output of the adder is the same data as 2xfs sampling. The two 48kHz sampled DAC can act as one 96kHz sampled DAC by an adder, not switch. If your sampling frequency is very high, It's advantageous.
Looking at the stuff people use in this thread, they're really non-standard stuff. Either fpga and solid, or too small to hand solder (for most), or different logic family/voltage levels etc.
This topic of what flip flop to pick has gone on and on in the DSC1 thread (or another one?), best you ask thereI'm afraid.
Last but not least: iirc the DSC1's usually use the HCT family, supposedly for lower distortion or other reasons, which seem to be hard to get.
Good luck Zoran!
In addition: it's highly unlikely that Tektronix uses cmos, so propably its some ecl family they use. Being ecl all signals are usually differential, so the rising edge of a clock can be just connected to the inverted clock input, it makes no difference for the flip flop, just a routing thing.
Thanks for the answers but I still can't fathom it's method of working - my main stumbling block being the negative phase output from one DAC? Sorry if I'm being stubbornly stupid.
But I found this Tektronix PDF (interleaved DACs in AWG a bit further) which explains in Fig 13 that the input signal is 1/2 clock delayed & phase shifted to the DAC which also runs on a delayed clock http://www.tek.com/dl/76W_29216_0_MR_Letter.pdf
Always another question though
- is this not the same as delaying by 1/2 clock, the neg phase analog output of a differential output DAC?Why isn't this a commonly used approach in DACs? As there ar eother stated advantages besides increased bandwidth according to Tek:
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