Musings on soekris Reference Dac Module

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ynmichael

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Joined 2015
TNT said:
I don't know. Do you?

//
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I think I have some idea of what everything else is on dam1021/1121. Seems that TI sells d-type flip-flops in that 5-leg package (apologize for sounding iffy again). I'm willing to bet money that Soren used post-FPGA reclocking for all his commercial products and dam19x1.


I need to measure dam1021 inferred jitter myself...let's hope emu0404 is up to snuff


I'm well-motivated to write a wiki that clarifies dam1021 has a jitter probably 100-1000x greater than the others.
 
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ynmichael

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Joined 2015
soekris said:
Let me put things strait, even as I have posted about it before:

On a Soekris DAC, the Audio input quickly goes into a FIFO with a size of 1mS samples, clocked by the input clock, which can have quite some jitter....

The reason for not using a large FIFO, like some other designs, is the delay though the system, I want to be able to support Video and Live Audio.

The clock is then recovered by a digital PLL controlling a very low jitter digital programmable clock generator. When detecting a new signal, that PLL start out with a fast filter, later switching to a slow filter with a 0.1 hz time constant, it will track the input clock down to about one sample precision. It works fine, as the used clokc generator can change frequency up to 1000 ppm without glitches.

The output from the fifo is clocked by the output word clock, the audio is then upsampled, first to 352K/384K in FIR1 filter, followed by a bank of IIR filters running at that clock, the IIR filter as default have the 2hz subsonic filter and a CD deemphasis filter. It's then upsampled to the final word clock at 2.8M/3.1M. On the first DAC, the dam1021, the wordclock is then output from the FPGA directly to the shift registers, adding the FPGA intricic jitter.

On all later models, incl. the dam1121, the word clock is then reclocked by a number of fast flipflops clocked directly form the master oscillator before feeding the shift registers, avoiding the FPGA fitter.

When decoding DSD, the FIR1 is replaced by a very fast parallel FIR lowpass filter, as decoding DSD is basically sending the bitsteam though a lowpass filter.

All internal processing is done at minimum 35 bit precision, the volume control is last in the chain before the audio is clipped as needed and rounded down to the number of bits in the R-2R networks.

"HDMI" audio, a useless nonstandard interface mostly use by less advanced DACs that don't have the FIFO and reclocking. That interface just use the HDMI cabling, don't have anything to do with real HDMI audio which are DRM protected. You can get small interface boards doing the RS422 to CMOS I2S recieving function.

The reason that new firmware for the dam1121 is not ready yet, is that the synchronous interface for multiple dam1121s, that complicates thing, don't make it impossible, it just require more changes in the FPGA code. It will be done at some time.
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Thanks a lot for the clarification Soren. Do you know if synchronization may be implemented in dam1021, perhaps reusing code from dam1121? Also, would dual-mono delay be reduced if input sampling rate is higher?
 
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ynmichael

Member
Joined 2015
living sounds said:
I haven't been able to detect any jitter either. It's a non-issue as far as I'm concerned.
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http://www.audiophilleo.com/zh_hk/docs/Dunn-AP-tn23.pdf

According to the model in the sidebar on page 15, 10khz audibility threshold is 50ps. Not sure if my calculation is 100% correct, I'm not very familiar with the relationship between ps-RMS and db.

Another source to the same argument: Audibility of Jitter - Page 2

I think Soren was too quick to dismiss the problem in this case, which is very possibly audible and not cost-prohibit to solve. This of course saved him trouble with firmware development and extra versioning if he improved the circuity in newer revisions. I can't change the facts, but I don't like it.
 
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soekris

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Joined 2009
soekris.dk
Paid Member
ynmichael said:
http://www.audiophilleo.com/zh_hk/docs/Dunn-AP-tn23.pdf

According to the model in the sidebar on page 15, 10khz audibility threshold is 50ps. Not sure if my calculation is 100% correct, I'm not very familiar with the relationship between ps-RMS and db.

Another source to the same argument: Audibility of Jitter - Page 2

I think Soren was too quick to dismiss the problem in this case, which is very possibly audible and not cost-prohibit to solve. This of course saved him trouble with firmware development and extra versioning if he improved the circuity in newer revisions. I can't change the facts, but I don't like it.
Click to expand...

It's not possible to change the clocking design on a dam1021, it's not firmware but hardware.... If you want better clocking, buy a dam1121 or dam19x1....
 
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ynmichael

Member
Joined 2015
soekris said:
It's not possible to change the clocking design on a dam1021, it's not firmware but hardware.... If you want better clocking, buy a dam1121 or dam19x1....
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I understand that the newer products are better designed after you took advice from forum members, and I think it's perfectly reasonable. But you could've made changes in the newer revisions of dam1021. You're still pushing out rev.5 that has the same problem. Am I wrong to assume that the main worry was firmware versioning and potential incompatibility with the other dam1021? Anyway, neither of us can change the situation now, unless you plan on making a new batch of dam1021. But I believe it is very important for this problem to be documented here so that others can make better informed decisions and make their own observations.

On a different note, would you be able to respond to my other questions regarding possible synchronized operation on dam1021? That is still remediable and entirely within the range of audibility tested by myself. Thanks
 
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ynmichael

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Joined 2015
Due to weather delays and sorting issues I won't get the EMU0404 until tomorrow... But I did receive the AnTek 10VA 2*6V toroidal transformer and it looks great. Longest diameter is still a couple of millimeter shorter than spec which makes for a perfect fit. The secondary wire leads are also surprisingly long so it saves the need for extension wires! It comes with a rubber pad and fits perfectly on top of the other toroidal. Only minor issue is that they seem to have placed the label upside down. As it is I would still wholeheartedly recommend it to anyone using the SK Lite kit as a low EMI xfmr replacement. With its size almost equaling the Talema 25VA, I'm sure that temperatures will be great too, certainly better than the 6VA UI laminate type that's speced at 110V.

Will have to trim the primary leads though; it's about 20cm too long right now.
 

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soekris

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soekris.dk
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ynmichael said:
I understand that the newer products are better designed after you took advice from forum members, and I think it's perfectly reasonable. But you could've made changes in the newer revisions of dam1021. You're still pushing out rev.5 that has the same problem. Am I wrong to assume that the main worry was firmware versioning and potential incompatibility with the other dam1021? Anyway, neither of us can change the situation now, unless you plan on making a new batch of dam1021. But I believe it is very important for this problem to be documented here so that others can make better informed decisions and make their own observations.

On a different note, would you be able to respond to my other questions regarding possible synchronized operation on dam1021? That is still remediable and entirely within the range of audibility tested by myself. Thanks
Click to expand...

There are no problems with the dam1021 design. I'm not planning to make any major hardware changes to older products as it will break firmware compatibility, like the dam1021 will never support connecting multiple dam1021's in a synchronous way. Like most other hardware manufacturers, I make new products which of course will include new ideas to improve performance, my resources is better used working that way.
 
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