Depends on if we're talking about an ideal person or myself
So I have had the wrong understanding of the word "You" all along
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Got 10/13 pval=4.6% and I'm convinced by the results. I had to take a break at 8/11 when I felt that I stopped hearing differences. My method was to try either one for a few times and assume it's center (0 us), then try the other and imagine that it's to the left (10 us/0.34cm), remember how confident I am about this and reverse the experiment to compare my confidence with the previous order. It works quite well.
Not going to try 5us for now. Soren, do you know how much delay is expected in dual-mono and how it relates to sampling rate, if it does? Also, is the delay random or is the top/bottom board more likely to have the delay? Thanks a bunch!
Not going to try 5us for now. Soren, do you know how much delay is expected in dual-mono and how it relates to sampling rate, if it does? Also, is the delay random or is the top/bottom board more likely to have the delay? Thanks a bunch!
I see you like staying up late. It's hard to resist sometimes.
I don't know what the level change is, but it's there... I'm not entirely sure how we perceive location, but level change and phase shift combined would probably produce a greater effect than phase shift alone?
On HA, folks found that even 5us is discernable... So I guess there's no point in testing further. It's pretty clear that we can tell very minute phase shifts...
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How it would affect me, if I didn't know about it and believed that it's perfect, it's probably as perfect as a synced system. I can probably put it out of my mind if I want to. But I am curious now if upsampling x8 would reduce the delay. If we can tell 1.5mm in our mental auditory image, I doubt we can tell 0.2mm (hopefully, if that's how sampling rate affects sync error...). In that case, I might initially be worried about the extra delay every time I use my phone as source. But, I can probably deal with it and would be happy that at least we have something of a solution with PC sources, which is what matters the most.
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TNT, I now realize you might've hoped that I would stop worrying about the uS interchannel delays altogether even though they are audible in ABX tests. My concern is that it is not so easy to anticipate all possible uses of the system in the long-term. A few uS probably won't matter when playing music, but what if you're using the system to perform ABX tests, such as interchannel delay? Further reduction in delay, if possible, may still be valuable, as well as better understanding of this problem. I'm also not sure that enumerating all possible uses of the DAC is reliably easier than maybe spending some time investigating possible remedies first. I hope I don't come across as unreasonably perfectionistic.
Soren, I believe many current and prospective dual-mono users would greatly appreciate it if you can provide some more details on how the delay is generated and whether there are ways to improve it, e.g. upsampling inputs? Thanks a lot!
Soren, I believe many current and prospective dual-mono users would greatly appreciate it if you can provide some more details on how the delay is generated and whether there are ways to improve it, e.g. upsampling inputs? Thanks a lot!
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The same problem perhaps exists for dual-mono dam1121 users who do not wish to invest in clock buffers for synchronous operation or who needs to keep the two boards relatively far apart. If upsampling helps it would also offer SPDIF users some serious (at least theoretical) benefits too with x4 sampling rate, even though x8 is only available with I2S.
Soren, any chance you might reconsider this on dam1021?...
Soekris' DAC implementations
Hard not to dream about being able to connect FPGA SLV and MCLK for sync before FIFO. 0.35uS in 44Khz, 0.044uS in 44x8...
I'll also volunteer to measure jitter impact if the second option is easier to implement...
What would be really cool is if we can switch the operations in firmware - minimize jitter imbalance for human uses, minimize delay for, idk, possible instrumentation purposes? It would make a really awesome DAC.
Soekris' DAC implementations
Hard not to dream about being able to connect FPGA SLV and MCLK for sync before FIFO. 0.35uS in 44Khz, 0.044uS in 44x8...
I'll also volunteer to measure jitter impact if the second option is easier to implement...
What would be really cool is if we can switch the operations in firmware - minimize jitter imbalance for human uses, minimize delay for, idk, possible instrumentation purposes? It would make a really awesome DAC.
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I run two 1121, 5 meter away using s/pdif so I'm in the situation you are debating. I don't doubt that you can hear the things you claim you do - I'm just not convinced that that test, with that stimuli, can be immediately transfered to the DAM and music listening. It seems you don't even know what the "fault" implies in reality. It's like in your car; is 50mph a little better than 51 mph... no wait, 49,5.... hmm. Don't forget to call the sound technician for all your CDs to see how they placed their mics! :-D
What I would worry about is if the inter channel delay varied during playback - I asked Sören and he said no. I'm good with that. A varying source clock would inflict a clock adjust in both DACs at the same time. But I would like to see clock changes in the command interface.
One must fight ones windmills. I'm pondering HF filter cap change despite of knowing better so who am I to judge
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What I would worry about is if the inter channel delay varied during playback - I asked Sören and he said no. I'm good with that. A varying source clock would inflict a clock adjust in both DACs at the same time. But I would like to see clock changes in the command interface.
One must fight ones windmills. I'm pondering HF filter cap change despite of knowing better so who am I to judge
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As I have said some time ago, async boards will follow each other down to less than one sample.... You can't in anyway hear that as it's fixed.
Those things have been discussed loooong time ago, start reading this thread form the start, or use the search function.
Anyway, I'll recommend new builders to use the new dam19x1 series....
All you said before was “a few uS” and it seems that we can hear differences down to 5uS, as far as anyone has tried. Maybe the difference we can distinguish is even finer but that would require a hi-res test track. Can you be a bit more specific about the delays caused by async operation? Is it typically one sample length - 5uS for 44.1 and 2.5uS for 88.2?
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