A flip-flop can be a re-klocker. No storage, "just" re-timing.
A FIFO in this context is a mamory. yes, like RAM. You write a number of 16 (24) bit words into it and you read them out at a later time. It should be obvious to anyone with basic knowledge about digital technology that if the incoming signal had any jitter (varying arrival time for the 16 bit words), it would be gone once you read out that same 16 bit word at a later time.
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A FIFO in this context is a mamory. yes, like RAM. You write a number of 16 (24) bit words into it and you read them out at a later time. It should be obvious to anyone with basic knowledge about digital technology that if the incoming signal had any jitter (varying arrival time for the 16 bit words), it would be gone once you read out that same 16 bit word at a later time.
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OK 1 ms. Jitter is about 1-100 ps arrival (to the memory) error. How does that survive a 16 bit word being stored for 1 ms?
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This is absolutely wrong - at least for s/pdif. You dont understand how it works.
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I just read this blog post, Synchronous Reclocking? | H i F i D U I N O
One thing I really don't understand is how Soren managed to reclock signal going into shift registers using Potato semi's flip-flops if the clock doesn't have traces going into the flip flops? Did I miss something in the circuits?
Also, I think I might've confused discussions of phase noise in the Si514 with that in the incoming clocks. Maybe. Regardless, measurements show no audible jitter, i.e. below -120db.
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Electrically things are probably isolated. But I think Soren said that the final clock will be synchronized to the incoming clock, in the sense that there will be no drift. He also said it allows for the use of the short FIFO compared to Ian's solution. I think it made sense to me.
And what is going on here?? Asynchronous reclocking
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Isolation has nothing to do with timing. Maybe you get it - but you express yourself in a "iffy" way... "drift"... "final clock"... but "the final clock will be synchronized to the incoming clock" is correct.
Do you understand why jitter can't pass a FIFO of 1 ms?
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Do you understand why jitter can't pass a FIFO of 1 ms?
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Jax describes the ultimate clock architecture:
"It's always better to clock the DAC first, then feed the clock back to the source. Any jitter from the source to the DAC will be limited to the clock itself near the DAC as long as no setup or hold times are violated."
Not possible for s/pdif if you dont have a very large FIFO like Ian. Can work for USB interface.
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"It's always better to clock the DAC first, then feed the clock back to the source. Any jitter from the source to the DAC will be limited to the clock itself near the DAC as long as no setup or hold times are violated."
Not possible for s/pdif if you dont have a very large FIFO like Ian. Can work for USB interface.
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If a flip-flop don't have an incoming clock it cant do re-clockig - thats for sure. Who said there weren't any traces? In the 1021 there is no re-clocking - the FPGA drives the ladders with the clock (and interrupts) it uses in its internal processing.
The 1121 do perform re-clocking between the FPGA and the ladders. I think its the only DAM that does it.
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The 1121 do perform re-clocking between the FPGA and the ladders. I think its the only DAM that does it.
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I can't see the traces but maybe they're on another layer. But can you input the clock to both FPGA and flip-flops? Just out of curiosity and would be nice to have the answer documented in this thread I guess... And don't forget about the new DAMs
Also, are you saying that 1121 avoids problem with FPGA jitter completely, so the ladder has exactly the clock jitter? I recall Soren's estimation of jitter from FPGA in dam1021 is in the hundreds of ps.
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I meant earlier that I found Jax's claim on the problems with async reclocking surprising. Supposedly, async should be perfect as long as you have a large FIFO to consume the clock differences right? Does it mean that there is an issue with Ian's design, or was Jax mistaken?
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If you read the thread *really* close you see that I actually proposed re-clocking south of the FPGA. Now, maybe he would have done it anyway. But to my best understanding he omitted it agin in later models - because he says that this actual function is what hinders him to release 1.20 for 1121.
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You were one of the first to try to get him to change his reclocking design, and the only one that's still here... I remember that
Hmmm. I do see ICs that look like flip-flops in his commercial models as well as dam1941. I find it hard to believe that he would go back to his hundred-ps jitter design. In any case, I find it a convincing reason that 1121 fw needs more time...
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