John Curl's Blowtorch preamplifier

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#16,824
Wavebourn said:


1. With all due respect, Sir, I have to point you back to the link that clearly illustrates complexity of speed related issues in semiconductors. You can always add and mix distortions for your taste and analyze what happen to them on different frequencies.

2. Edit: closer to the discussion, Miller capacitance in transistors is not a capacitance actually.
Click to expand...

1. :bs:
2. :bs:
 
#16,825
It was about 30 years ago when Prof. Shirokov in TIASUR taught us physics of semiconductors, but I still remember that there is a big difference between non-linear dynamic charge effects and capacitances between metals in vacuum.

Edit: that's why I am always tempted to put your favorite flag:
bs.gif
when somebody using lots of transistors is afraid of dielectric absorption in capacitors. 😀
 
#16,832
Re: VAS fighting

Edmond Stuart said:


Hi Glen,

You are right, hardly any VAS fighting IF if the gain is considerably reduced (i.e. crippled) by terminating the inputs (of the VASes) with a low impedance (1k). However, this is what Bob said (bold font by me):

"The effect may be worse when the VAS is very un-crippled, with a very high impednace at its input (VAS transistors with emitter followers in front of them, stabilized helpered current mirrored loads top and bottom of the input LTPs)."

See below how devastating it can be.

Cheers,
Edmond.

edit: dumb question, what's that APT1 thingie? Does somebody have a link to the schematic?
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Geezz has this thread taken off since I was here yesterday.

No argument here, but Bob (as far as I can see) was talking about typical amplifiers as well.

We can also discount the ones with "very un-crippled" VAS stages from a disussion on typical full comp. amplifiers because these simply do no work in real life - DC bias instability of the VAS will kill the performance well ahead of Miller cap fighting.
Of course this can be rectified with a CMCL, but then the Miller cap issue isn't an issue any more.

Cheers,
Glen
 
#16,833
Wavebourn said:
It was about 30 years ago when Prof. Shirokov in TIASUR taught us physics of semiconductors, but I still remember that there is a big difference between non-linear dynamic charge effects and capacitances between metals in vacuum.

Edit: that's why I am always tempted to put your favorite flag:
bs.gif
when somebody using lots of transistors is afraid of dielectric absorption in capacitors. 😀
Click to expand...

Don't worry, your recollection is just a little cloudy that's all. Ovidiu is your man on this. I think your gist is right, but the details are a little more complicated. There are basically two types of capacitance in a BJT - junction capacitance (sort of akin to a plate capacitor) and diffusion capacitance which is to do with minority charge carrier injection. The former dominates in the reverse-biased CB junction and the latter in the forward-biased BE junction. You are right that neither are much like the capacitance between electrodes in a tube. They are about as linear as a bent coat hanger. Transistors are a complete pain in the ****. Darned things!
 
#16,834
by stinius -What is the difference between a Resistance (R) and an Impedance (Z) ?
Click to expand...

I know R and Z
Z= opposition to AC , a varient of the concept of resistance as it
applies to ac.
R ? if I didn't know this , please take my 2kva toroids
away so I don't kill myself. :bigeyes:

What is "J" ..joke?

Put a man on
the moon ??.. we outsourced that one to the india and
the chinese. 🙂
OS
 
#16,835
ostripper said:


What are they?, maybe just the biggest ones for those of us
with less understanding..
OS

Edit- I noticed it went from "several" to "few" , all I want
is to get it to "none" or "insignificant" , and
maybe increase the "understanding"
Click to expand...


Less input bias current.

No need for an intermediate small-signal, or level shifting stage that that has to cop the full +/- supply rail voltage.

Cheers,
Glen
 
#16,836
ostripper said:


I know R and Z
Z= opposition to AC , a varient of the concept of resistance as it
applies to ac.
R ? if I didn't know this , please take my 2kva toroids
away so I don't kill myself. :bigeyes:

What is "J" ..joke?

OS
Click to expand...


You don’t get it.
John is running the class here; I’m not a TA so I leave it to the master and his TA (PMA) to explain it.
 
#16,837
By GK -Less input bias current.
Click to expand...
?? That would be the advantage of an EF'ed VAS ?
Too few words there..

No need for an intermediate small-signal, or level shifting stage that that has to cop the full +/- supply rail voltage
Click to expand...

That is not a neccessarily a "flaw" ,as long as the devices
are low Cob / high Vce. In fact with cascodes and a SMD
npn/npn one chip LTP , I have perfect symmetry + no fighting.
I DO admit the original APT was crude (simple CM) , but
better devices do wonders for a design.
OS
 
#16,838
Bob Cordell said:



Hi Glen,

You are largely correct, and I did go back and check some of my simulations last night. I have good news and bad news. First, the bad news is that the effect I described is very real. The good news is that I observed it in what I consider to be a bit of an extreme case, in terms of very high impedance at the input node of the two VASs. This matters a lot, because the output impedance due to the shunt feedback from the Miller capacitor depends largely on the voltage divder ratio it sees between the impedance of the Miller capacitor and the other node impedance on the VAS input node. The lower the impedance on the VAS input node, the less is this effect. In the design I quoted last night, that node impedance was on the order of 50-100k. I have since simulated with a more realistic impedance of 5-10k, and the effect is reduced, but still see-able.

One thing to look at is the VAS emitter degeneration resistor signal current with the Miller caps perfectly matched, and then with them at +/- 20 %. If you see increase VAS signal current as a result of the mismatch, you are seeing the effect. If/when this current gets big enough, the VAS transistor can go into cutoff. I'll try to post a sim when I get a chance.

This effect is also brought on by gm mismatch in the P/N differential pairs, and that is why I agree with you that complementary JFETs are not a good choice for this topology in designs that are susceptible to the effect I describe. Again, I don't think the JC1 is susceptible to this concern.

Cheers,
Bob
Click to expand...


Hi Bob.

I'm not surprised that the effect was great with 100k loads for the LTP's. However, such an amplifier has other issues that make it impractical. The DC bias stability of the VAS would be very much upset by even the slightest current imbalance in the LTP's (due to the huge input stage gain) - so much so that the amp wouldn't work in real life with out the additional complexity of a CMCL.

Cheers,
Glen
 
#16,839
ostripper said:

?? That would be the advantage of an EF'ed VAS ?
Too few words there.. That is not a neccessarily a "flaw" ,as long as the devices are low Cob / high Vce. In fact with cascodes and a SMD npn/npn one chip LTP , I have perfect symmetry + no fighting. I DO admit the original APT was crude (simple CM) , but
better devices do wonders for a design.
OS
Click to expand...


Arguing with you is largely pointless because you always conjure up simulation experiences that support your preconceived notions (“Blameless” topology limiting 1kHz THD to 0.01%, LTspice backing up the linearity and non-switching claims made for a certain OPS.....) But anyway.....
EF'ed VAS? What ARE you talking about?
The leach topology does not need the crappy intermediate stage. Period. As for "perfect symmetry + no fighting" these things only exist in simulation land and there can be made applicable to just about any amplifier topology. I can get "perfect symmetry" with the Leach in sim much easier than the APT1. Wow!
 
#16,840
Arguing with you is largely pointless because you always conjure up simulation experiences that support your preconceived notions
Click to expand...

I never conjure up ANYTHING. My preconceived notions are always
subject to change , unlike yours.
A "blameless" run just short of clipping at 100w ,will, in the real
world give at least .01%THD20. I run my sims in a "worst case"
scenario.

So I guess arguing with you would be pointless as you
are on a stiff high horse and make 4 word statements
like "Less input bias current"(leach or apt?) ,making no reference to anything. Not all of us can read minds across the globe.
OS
 
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