Is the UcD modulation scheme less than optimum?

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Originally posted by Charles (phase_accurate)
There is one thing about that leapfrog simulations that looks suspicious: Why does a symmetrical circuit generate even order harmonics?

Hi Charles,

It seems both the UcD and CFH-leapfrog exhibit even order harmonics because the extreme dc bias causes one side of the much smaller ac to distort much more than the other side does (it doesn't come as near to the rail).  I'd say UcD has more even order distortion because it suffers a greater frequency droop near the rails.  If leapfrog performs a bit better, it's not because of its "leapfrogness", rather it's because of the extra added circuitry that better anchors the frequency of the hysteresis oscillation topology.

Regards -- analogspiceman
 
Originally posted by Portlandmike


On your comment about the distortion being mostly due to the frequency shift, that's interesting. I've been simulating different modulators with complex poles and zeros to make the loop less insensitive to this. I did this awhile back, but thought maybe this wouldn't help since lower frequency in my experience meant less distortion because of less error pulses.... but the UcD driver topology seems to minimize this affect, so maybe it is an issue.

Yes, this does seem to be an issue for best large signal performance.  It would be very interesting to search for a "better" compensation scheme than delay plus one or two real-axis high frequency poles.  Remember, it is quick phase shift around the oscillation frequency that would minimize shift - gain bumps don't matter so much as long as there is enough to ensure saturation (the AGC mechanism). - a.s.

PS: Also need to look to maximize audio loop gain...
 
Remember, it is quick phase shift around the oscillation frequency that would minimize shift - gain bumps don't matter so much as long as there is enough to ensure saturation (the AGC mechanism). - a.s.

Like a 2nd order allpass with a high Q for instance.
I tried this with the topology I posted in this thread but it didn't improve things. Interestingly the contrary seems to be the case. Two lag filters (which are not famous for quick phase shift) instead of ordinary lowpass filters gave about half an octave of carrier drift. Ordinary LPF gave more frequency shift.

Regards

Charles
 
My memory must be playing tricks with me. I now "tested" the topology with a 2nd order allpass once again.
The carrier is indeed very stable (90 % modulation shown !) and k3 for instance is down by about 10 dB. But the spectral distribution of THD looks less nice than the lag filter version.

Regards

Charles

Edit: Had to "repair" attachment
 

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Had a closer look at the bahaviour of the amp with the allpass. While the average switching frequency stayed fairly stable there were some glitches at high modulation depth which I don't like that much.
So it might not be a too good idea to force an amp to switch at a constant frequency by all means.

Regards

Charles
 
Originally posted by Charles (phase_accurate)

Had a closer look at the behavior of the amp with the all-pass. While the average switching frequency stayed fairly stable there were some glitches at high modulation depth which I don't like that much.
So it might not be a too good idea to force an amp to switch at a constant frequency by all means.

But it's probably a good idea to force it to do so by the right means. :smash:

Charles, could you please elucidate a bit on the glitches you saw?

By the way, for the LTspicers out there who would like to share in the fun, I’m attaching my simulation files.  Along with the two amplifier schematics are plot setting files that will rescale the x and y axes after running an FFT (hint: it's a dropdown menu item).  There also is an EQ schematic that is set up to compare the frequency response of the two amplifiers via a swept sine source (must be sure the FFTs are comparing apples to apples, eh?). :Pinoc:

Regards -- analogspiceman
 

Attachments

Analong Spice Man,

Thanks for the files.

Phase accurate.

If your up to it, try using fb like:

complex zeros at 60k with a Q of 0.7.
Complex poles at 600k with a Q of 1.4.
simple pole at 60k.
Simple zero at 600k.

It should have a more stable switching frequency, and maintain higher loop gain when it does dip compared to the stock, zero at 60k, pole at 600k. low freq loop gain is almost the same.

Mike
 
Originally posted by Portlandmike

... try using fb like:

complex zeros at 60k with a Q of 0.7,
complex poles at 600k with a Q of 1.4,
simple pole at 60k,
simple zero at 600k.

It should have a more stable switching frequency, and maintain higher loop gain when it does dip compared to the stock, zero at 60k, pole at 600k and low freq loop gain is almost the same.

I ran the transfer function using your suggested root locations (using LTspice's Laplace capability), and from the resulting phase characteristic, I'm guessing you formulated your network to work with the typical UcD power stage delay (somewhere around 135ns).  By accepting a little more wobble in the magnitude (and why not? there's plenty of available gain) one could bump up the Q's for more rapid phase shift and less frequency droop as the amplifier output approached the rails.

With Q's increased to 1 and 2, I had to drop the poles and zeros a bit (40kHz/400kHz) in order to match my "standard" UcD simulation's quiescent operating frequency.  It was surprisingly difficult to come up with a lumped element (Rs, Ls and Cs) feedback network to run the transient simulation, and, although LTspice was happy with it, it wasn't at all production practical. :scratch2:

Okay, now to the good stuff - the idea seems to work remarkably well.  Frequency droop was less than 20 percent until almost right on the rails - more than twice as good as the stock UcD topology (seemed to be free of pulse skipping that Charles observed as well).  Maybe this is something Bruno and Company should look into (assuming the rest of the audio performance characteristics are the same or improved, of course). :tilt:

By the way, if you have worked out a good solution for a practical feedback network, I'd love to see it. :magnify:

Regards -- analogspiceman
 
analogspiceman said:


I ran the transfer function using your suggested root locations (using LTspice's Laplace capability), and from the resulting phase characteristic, I'm guessing you formulated your network to work with the typical UcD power stage delay (somewhere around 135ns).  By accepting a little more wobble in the magnitude (and why not? there's plenty of available gain) one could bump up the Q's for more rapid phase shift and less frequency droop as the amplifier output approached the rails.

With Q's increased to 1 and 2, I had to drop the poles and zeros a bit (40kHz/400kHz) in order to match my "standard" UcD simulation's quiescent operating frequency.  It was surprisingly difficult to come up with a lumped element (Rs, Ls and Cs) feedback network to run the transient simulation, and, although LTspice was happy with it, it wasn't at all production practical. :scratch2:

Okay, now to the good stuff - the idea seems to work remarkably well.  Frequency droop was less than 20 percent until almost right on the rails - more than twice as good as the stock UcD topology (seemed to be free of pulse skipping that Charles observed as well).  Maybe this is something Bruno and Company should look into (assuming the rest of the audio performance characteristics are the same or improved, of course). :tilt:

By the way, if you have worked out a good solution for a practical feedback network, I'd love to see it. :magnify:

Regards -- analogspiceman


I used 210nS from the Bruno's AES paper, so no doubt it can be optimized. No doubt that's why different pole zero locations worked better. On higher Q's, especially at the zero, be careful that at no load, the phase shift doesn't exceed 180, or a real amp will blow up I suspect! :hot:
If its perfect cancelation of the LC poles, then its safe, but Murphy live's.
As for production, I routinely realize complex poles and zero's with a simple buffer. I haven't tried to realize all 3 poles and zero's, but I think I can. I've been playing way to much hooky on UcD lately. Got some good power supply stuff I want to prove.
My favorite buffer is a simple MPSA18 high gain NPN loaded by another MPSA18 current source. Key is the current source for good sound, and also slightly better measurements. My current source is very simple, and most will dismiss it, but its as follows. Run the current source with lots of voltage on the Re. I usually pick half the negative rail. The part that most will choke on is the bias is a simple divider with a thevinin equivelent of twice Re. This is listened in, and it measures slightly better than other dividers or bias schemes, and is about an order of magnetude better sounding than a zener or stiff current source bias. Adding a cap to the base of the current source and tail of Re seems to make engineering sense, but its a negative. Not sure the mechanism, but i've been told it actually simulates true too. It was listened in on my side, and measurements supported it, although it was at the limits of the measurement equipment.
I just measured the buffer circuit again with my AP ATS-2, and it brought it to its knees. The harmonic content was down over 100db 20-20k, and if 2nd harmonic is removed, its down more than 110dB, the limits of the equipment.

Use two buffers, two PF4 Salen and Key twin Tee's, and a simple pole zero and I suspect its very realizable, and if the simple poles are first, then the dynamic range of the buffer is quite small, like down 20dB over full swing.
But, I need to look at this a bit more and I'll forward the results.
I think I simulated this early on, but I need dig it up.

Thanks for the sim support. I was kind of hoping for that 🙂

Mike

p.s. You might just try both complex poles and zero's at 400kHz.
Like Qp's of 1.4 or whatever, and zero's with Q's less than Qp, maybe half or 1/3'rd. Haven't matlabed it, but I suspect that will be very easy to synthesize.
 
Originally posted by Charles (phase_accurate)

Had a closer look at the bahaviour of the amp with the all-pass. While the average switching frequency stayed fairly stable there were some glitches at high modulation depth which I don't like that much.

After experimenting a bit with various feedback networks, I've been able to reproduce very nasty glitches at high modulation depth and, what's worse, a time dependent non linear gain characteristic even at relatively non large signals.  Clearly the choice of feedback poles and zeros and their Qs is critical to achieving a balance between distortion from this effect and distortion from frequency droop.  It seems the feedback filters should settle out very nearly within one cycle, something that, as far as I know, is at odds with the high Q networks required to achieve the rapid phase change necessary for minimum shift of the frequency of self oscillation.

This engineering dilemma could be a very interesting optimization problem.  I'm guessing that one could do better than the UcD in that regard (though not by much).

Regards -- analogspiceman
 
It is questionable if it would make much sense at all (apart from being a sales argument) to have constant THD up to almost full output power.

If an amp is regularly driven at more than 10% of its nominal power than you either have

- a severely underdimensioned amp
- or an application where 0.1 % of THD doesn't matter at all.


Regards

Charles
 
koolkid731 said:
In an SOA, switching frequency can't be constant when M approaches 1 due to minimum pulse width, i.e. not narrower than x seconds, while D approaches 1. Therefore the switchinbg period is x/(1-d).

How does one attach an LTSpice plot?


Sure the swithing frequency can be constant.
Not a problem, the issue is the maximum output is then:
Dmin/(2*fs) for single ended.
If the minimum pulse is small, say 5%, then its not a big deal, you just only get 90% of rails, which is like 1dB down. Not much room for improvement.

Mike
 
analogspiceman said:


After experimenting a bit with various feedback networks, I've been able to reproduce very nasty glitches at high modulation depth and, what's worse, a time dependent non linear gain characteristic even at relatively non large signals.  Clearly the choice of feedback poles and zeros and their Qs is critical to achieving a balance between distortion from this effect and distortion from frequency droop.  It seems the feedback filters should settle out very nearly within one cycle, something that, as far as I know, is at odds with the high Q networks required to achieve the rapid phase change necessary for minimum shift of the frequency of self oscillation.

This engineering dilemma could be a very interesting optimization problem.  I'm guessing that one could do better than the UcD in that regard (though not by much).

Regards -- analogspiceman

Not sure about the assumption of needing to settle in one cycle.
If its poles are approximately the fs, then that's way out of band.
The metric might be more like 10 nominal cycles.
After all, there are whole classes of D/A's that use that philosophy.

Mike
 
Leapfrog control vs voltage feedback SOA

Leapfrog control method does keep the switching frequency of self-oscillating amplifiers SOA within a narrower range. However, comparable simulations have shown that from pure THD standpoint, voltage feedback only can achieve lower THD than "leapfrog".

The best performance so far for 2nd harmonic distortion of a 20kHz input for 95% of max output is -102dB, or less than 0.001%. Your milage will vary 🙂

The circuit includes real op amps and comparators from Linear Tech 🙁

It's possible Leapfrog control method (which is actually not new, as current-mode control ICs galore) provides better sound due to narrower switching frequency range and somewhat lower output impedance.
 
Re: Leapfrog control vs voltage feedback SOA

koolkid731 said:

Leapfrog control method does keep the switching frequency of self-oscillating amplifiers SOA within a narrower range. However, comparable simulations have shown that from pure THD standpoint, voltage feedback only can achieve lower THD than "leapfrog".
[...]
It's possible Leapfrog control method (which is actually not new, as current-mode control ICs galore) provides better sound due to narrower switching frequency range and somewhat lower output impedance.

If leapfrog measures worse it's only because it's more difficult to get a high fidelity current feedback signal than it is with voltage feedback.  There should be nothing inherently more prone to THD about leapfrog (less, in fact if you consider overload behavior).

As a generalized approach, leapfrog is new because it allows for any number of rungs on the low pass output filter ladder.  Also, it is way more than simple current mode control as it achieves the optimum combination of feedback and feedforward from the output filter.  And unlike with simple current mode control, where Rs and Cs stand in as an approximation of the state of the output filter, with leapfrog the output filter is the compensation network - there are no rail sticking errors.

Regards -- analogspiceman
 
analogspiceman said:
Okay, this should link you to the gif of the UcD FFT for easy armchair comparison to the (attached) FFT of the leapfrog (nearly) constant frequency hysteresis class-d amplifier. – a.s.

THD @ constant power as a function of DC offset is an interesing way of exploring distortion. Thank you for opening my eyes analogspiceman. I think that this method can show some difference between phase and hysteresis modulated amps (nonlinear vs. ~linear carrier waveform). In general this migh reveal, what some listening test has showed, namely that some amplifiers mesure well, but sound bad.
I also like Bruno's idea about a flat THD response.
 
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