I onl had to slightly bend one pin, c2(which seemed offset from the rest) and then it basically dropped in.
@richmain - definitely what @MEPER said. There is only one correct orientation. It's a snug fit, but if the pins are straight it shouldn't take a lot of pressure.
Attached is the datasheet for the transformers. DO NOT go by the orientation of the silkscreen / lettering. It is not consistent across all parts. ONLY go by the two pins that are placed closer together to determine pin #1.
Attached is the datasheet for the transformers. DO NOT go by the orientation of the silkscreen / lettering. It is not consistent across all parts. ONLY go by the two pins that are placed closer together to determine pin #1.
I received by 2 x P+N JFET octets from "ebay Punky" for BAL IP.
I have double up as I want to try out "parallel" JFETs.
I noticed some metal cans also included. I assume those are meant to be put around N+P pairs to thermal couple them close?
Not something we want to do in IP implementation?
Just for curiosity......how do you mount these cans? .....thermal glue? .....I guess then you also mount N+P "face2face"?
I keep those cans for a future project.......
I have double up as I want to try out "parallel" JFETs.
I noticed some metal cans also included. I assume those are meant to be put around N+P pairs to thermal couple them close?
Not something we want to do in IP implementation?
Just for curiosity......how do you mount these cans? .....thermal glue? .....I guess then you also mount N+P "face2face"?
I keep those cans for a future project.......
Attachments
put some thermal paste in can, mount on pair of devices as hat
use your sense of ingeniousnessssssssss ........ it's really simple as putting hat on your head
mad ones already injected all necessary wit in product, per se
use your sense of ingeniousnessssssssss ........ it's really simple as putting hat on your head
mad ones already injected all necessary wit in product, per se
Oh oh, another ookup maybe?
Channel one is ready to go, channel two had initial offset of -90mv on positive signal of bal IP. Trimming down with p3 (or up) is only possible to -28mv. Any pointers as to where to look?
PSU side is fine with both easily set at +-15v
Channel one is ready to go, channel two had initial offset of -90mv on positive signal of bal IP. Trimming down with p3 (or up) is only possible to -28mv. Any pointers as to where to look?
PSU side is fine with both easily set at +-15v
hope you didn't mixed JFet pairs
pull them all out from that channel and measure Idss, then pair them
that- if you didn't made any ookup around
pull them all out from that channel and measure Idss, then pair them
that- if you didn't made any ookup around
One good reason to use the 370s / J74s in the kit... easy to see difference 🙂
I used one quad set from the store, between those it does not matter if they match between pos and neg half of channel, correct?
J1 and 2 are correct (and 3 and 4).
J1 and 2 are correct (and 3 and 4).
Well, I cleaned the board on the back with defluxer and was able to correct offset, or so I thought. Putting it back in place and now behaviour is back. I will have to continue with thorough investigation and maybe reflowing solder pads.
I thought I'd quickly put it together before my herniated disk surgery tomorrow. That rarely is a good idea😅
I thought I'd quickly put it together before my herniated disk surgery tomorrow. That rarely is a good idea😅
None that I could find, but I bought the IronPre chassis Gianluca so kindly donated so I’ll definitely bring one (or two) next year 👍
I have brought Yageo resistors from Mouser are they good enough never heard of them before, or should i look for something better.