Implementing a true FIFO buffer with low phase noise clock on the Soekris DAM1021 DAC

[TNT]

You are not confusing fifo buffer with re-clocking?

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[andrea_mori]

Well, we deal hear with PCM and not DSD or I am wrong? While on PCM samples counts..

So at the end of the day we deal with samples given at LR-Clock at sample rate.

Also using samples, so we have to calculate 8M (bits) / 8 (bits/byte) / 4 (bytes per sample)

I have already explained the math, what is not clear?

 

[BesPav]

Maybe the answer is: the samples reside in RAM.

No.
CPLD generates very fast signal at its output, an order faster than input I2S stream, so it inputs an additional samples based on some interpolation math inside it and you anyway can't stop it to do this.

 

[andrea_mori]

Not really, I believe you have not clear how the FIFO (our FIFO ) works.

Please, take a look at this link
The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker

It's a dedicated thread about the FIFO.

 

[TNT]

You are confusing something. I'm not quite sure what. A fifo buffer has about the same in and out speed - they differ some 50 ppm maybe. The differ exactly as much as the incoming and the outgoing clock differ.

Jitter is not even a consideration in a fifo buffer. That comes later on and must be taken care of with re-clocking anyways. No jitter problem while in PCM... only calculation errors. Jitter is relevant at point of D/A conversion and its associated with the clock, not the data (pcm samples).

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[andrea_mori]

No.
CPLD generates very fast signal at its output, an order faster than input I2S stream, so it inputs an additional samples based on some interpolation math inside it and you anyway can't stop it to do this.

FPGA speed is determined by the output sample rate, the format and the bit depth.

The FPGA has no intrinsic speed, it needs a clock to work.

 

[TNT]

No.
CPLD generates very fast signal at its output, an order faster than input I2S stream, so it inputs an additional samples based on some interpolation math inside it and you anyway can't stop it to do this.

You agreed on bit transparent but still claim you have interpolation errors - how dos that go together?

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[BesPav]

FPGA speed is determined by the output sample rate, the format and the bit depth.

Yes, output bit depth in this case is 1, now measure speed and think why you need a FIFO there.

You agreed on bit transparent but still claim you have interpolation errors - how dos that go together?

No, man, CPLD outputs a much faster signal than input is. So there are no way not to interpolate input signal and such an interpolation occurs anyway not matter what a time domain difference present or not.
This is just how such a DAC works.

 

[andrea_mori]

You are confusing with PWM DAC where the interpolation is needed, the FIFO buffer is not a DAC so it does not perform any interpolation.

 

[BesPav]

You are confusing with PWM DAC where the interpolation is needed, the FIFO buffer is not a DAC so it does not perform any interpolation.

Oh, Andrea, please, keep me from facepalming today.
You're trying to attach FIFO buffer to such a DAC. It doesn't benefit from doing this.

 

[andrea_mori]

And why?

The DAM1021 is a R2R PCM DAC not a PWM DAC.

The benefit of the FIFO buffer is that the DAC is not affected by the jitter of the source because they work in different time domains and the output of the FIFO is clocked by a very low phase noise oscillator.

 

[TNT]

When (if?) you get this to play, how do you know what an eventual difference in sound come from - you have to create new filters, OS (?) etc which maybe has more effect on SQ than jitter...

Whats your thoughts on this Andrea?

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[BesPav]

The DAM1021 is a R2R PCM DAC not a PWM DAC

Non oversampling?

 

[andrea_mori]

When (if?) you get this to play, how do you know what an eventual difference in sound come from - you have to create new filters, OS (?) etc which maybe has more effect on SQ than jitter...

Whats your thoughts on this Andrea?

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The FIFO Lite does not implement filter so the DAC plays exactly the input converted to 24 bit (28 but the last 4 LSB will be all zeros since there is no digital volume control).

Oversampling has to be implemented in the source if needed.

 

[andrea_mori]

Non oversampling?

No, it's a FIFO buffer not a digital filter.

 

[BesPav]

No, it's a FIFO buffer not a digital filter.

DAC are oversampling!
How it do this?

 

[TNT]

The FIFO Lite does not implement filter so the DAC plays exactly the input converted to 24 bit (28 but the last 4 LSB will be all zeros since there is no digital volume control).

Oversampling has to be implemented in the source if needed.

I was talking about your modified DAM. But maybe you are saying that you will use your "Lite" to drive the DAM ladder?

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[TNT]

Aha - Fifo Lite.

How to campare if the new clock improves things?

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[andrea_mori]

DAC are oversampling!
How it do this?

R2R PCM DAC are not oversampling, do you know how a R2R ladder works?

You can add oversampling before the conversion, not in the R2R ladder that's PCM and not PWM.

Again, you are confusing PCM with PWM, the DAM1021 is not a delta-sigma DAC like the ESS DAC.

 

[andrea_mori]

I was talking about your modified DAM. But maybe you are saying that you will use your "Lite" to drive the DAM ladder?

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Yes, since the DAM1021 needs a custom protocol I have to use my FIFO Lite to drive its switches/ladders.

With a little update in the FPGA firmware.