I start this thread to investigate the opportunity to install a true FIFO buffer on Soekris DAC.
If the sound improves I will provide a interface board and detailed instruction to install the device for those who already owns the DAC.
The true FIFO adds latency so the audio from the DAC will be no longer synchronizable with movies.
If the sound improves I will provide a interface board and detailed instruction to install the device for those who already owns the DAC.
The true FIFO adds latency so the audio from the DAC will be no longer synchronizable with movies.
Don't worry, although the designer won't help I will found by myself how to update the DAC.
It's not much different from my new DAC Lite although I use a totally different front end and a segmented architecture.
An interface board will be needed because the shift registers of the DAC are fed in parallel (4 lines) while the output of my new FIFO Lite is serial.
Have a nice Xmas you too.
It's not much different from my new DAC Lite although I use a totally different front end and a segmented architecture.
An interface board will be needed because the shift registers of the DAC are fed in parallel (4 lines) while the output of my new FIFO Lite is serial.
Have a nice Xmas you too.
I don't know if it will worth, maybe for those who already owns the DAC.
I know I will throw out all the front end, but as I said several times the architecture IMHO is totally wrong if one would listen to music.
The true key of the FIFO is isolating the DAC from the source and reclock the DAC with better clock.
It's not possible with the actual architecture of the DAM.
Moreover I cannot update the firmware of the FPGA and the micro because I don't own the source code.
So the only chance is just to replace all the front end.
You save the power supply, the switches and the ladder resistors, I think more than 50% of the board cost, maybe more.
Our new DAC Lite does not support anything because it needs the new FIFO Lite to feed it, since it use a custom PCM protocol.
The new FIFO Lite has 4 selectable I2S input, so you can use whatever you want with I2S output.
If you like to use USB you can use the Amanero, the WaveIO, the JLSounds interfaces and so on, although we will provide our USB to I2S interface.
The real advantage of the new FIFO Lite is that it should really isolate the DAC from the source, so the DAC will be no longer source dependent.
What are you throwing out?
- 1 x SI514 5 EUR
- 1 x SPARTAN6 22 EUR
- 1 x STM32F030K6T6 1 EUR
- 1 x LD1117 0.3 EUR
- 2 x L7905 1 EUR
- 1 x ICL3221ECVZ 1 EUR
- 3 x SI8620 2.4 EUR
- 1 x W25Q80DV 0.3 EUR
The total amount is 33 EUR, add a few resistors, capacitors and so on and the final cost is around 35 EUR.
Not much for a 350 EUR board.
You can find the block diagram at the following link
The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker
Yes, the FIFO buffer is balanced when there is no music.
The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker
Yes, the FIFO buffer is balanced when there is no music.
For me, the beef question remains: How you sync the Output MCK to the Input MCK
without loosing any samples 
For me, the beef question remains: How you sync the Output MCK to the Input MCK
A fifo buffer has storage capacity for a second worth of music. This is enough to digest the speed differences. On song start we fill the buffer half up using the external incoming MCK and then play-out starts. Play-out uses the internal MCK. Hopefully, the differences between the 2 MCK is not so big that the stored music is enough to sustain an uninterrupted play-out. So MCKs are not synced and thats the whole benefit of a fifo buffer - one can use a much better internal MCK - it works.
//
In our new FIFO Lite we use a 8Mbit SDRAM so there is enough room to bufferize the incoming data (although the latency is configurable to 1, 2, 4 and 8Mbit).
Moreover the buffer is balanced as soon as there is no music at the input.
So, as TNT pointed out, the input MCLK is not synchronous with the output MCLK, that's just how a FIFO buffer works.
The FIFO is asynchronous and its timing comes from a low phase noise master clock oscillator.
This means that the DAC will be no longer source dependent.
Moreover the buffer is balanced as soon as there is no music at the input.
So, as TNT pointed out, the input MCLK is not synchronous with the output MCLK, that's just how a FIFO buffer works.
The FIFO is asynchronous and its timing comes from a low phase noise master clock oscillator.
This means that the DAC will be no longer source dependent.
OK, no sync, no SRC as ESS ..
so we need to fill 1/2 of the buffer to have to deal with secure underflow & overflow behaviors.
This means after 4M Samples we get for sure a sample overflow or underflow. All dependent, when this happens, of the +/- 0..100ppm master clocks accuracy & given SR. For sure, at higher SR, it will occur more often!
Also the question will be how long your samples are, as up to may 30 minutes.
So you may calculate using SR 44.1 .. xxx kHz with 4M samples and up to 100ppm off
Or I am wrong
This means for SR 44.1kHz & 4M samples and higher sample count: To wait 1.5 Minutes to play
Also, on lower samples as 1..2 minutes, some space management is required while getting a space, but still to play 4M samples
Interesting for a side project:
. while the incoming I2S have to be converted to parallel for the FIFO RAM banks using a controller anyway or not?
. interesting would be to use the parallel interface with high xx MHz SR to sample from a fast ADC to the FIFO and reading with a known audio I2C to a lower SR SPDIF >> USB interface.
. May Fre and others may love it
. But the maximal parallel input frq. should be known
. In other words as the DSO do
OK, no sync, no SRC as ESS ..
so we need to fill 1/2 of the buffer to have to deal with secure underflow & overflow behaviors.
This means after 4M Samples we get for sure a sample overflow or underflow. All dependent, when this happens, of the +/- 0..100ppm master clocks accuracy & given SR. For sure, at higher SR, it will occur more often!
Also the question will be how long your samples are, as up to may 30 minutes.
So you may calculate using SR 44.1 .. xxx kHz with 4M samples and up to 100ppm off
Or I am wrong
Let assume 44.1 kHz sample rate, I2S full 32 bit (the worst case), so 44100 x 64 = 2822400 bit per second.
Using 8Mb SRAM you get around 2.9 seconds stored in the buffer: 8192000 / 2822400 = 2.902494....
Assuming 100ppm of frequency deviation you loose around 283 bit per second: 2822400 x 100 / 1000000 = 282.24
So the buffer will be full or empty after around 8 hours: 8192000 / 283 = 28946.996 seconds, or 482.45 minutes or 8.040832 hours.
Then around 4 hours with the latency set to 4 Mb, 2 hours to 2 Mb and 1 hour to 1 Mb (assuming no buffer balancing along 8, 4, 2 or 1 hour).
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