My first point adressed the problem that the PN curves where for different frequencies i.e. the 6dB/oct decrease in PN with half the frequency was not taking into account.. i.e. you compared pn for 2 clocks with different frequency.
Sorry - yes you named the sources.
How does fiforpi and RPI in the last chart relate? Is it:
- AUNE X5S SD card player for S/PDIF - is this fiforpi?
- RPI 4 standalone source for I2S - is the RPI?
I don't question your listening impression (it not possible to deny a persons experience)
You see, there is a problem with the DAM DPLL that you may have heard about - it varies its clock every second or 10 seconds or 2 times a second so it is hard to do comparisons from different moment in time - 1 minute, 20 minutes... this can complicate comparisons - one would have to have both input and output PN measured at the same time to be sure what is compared.
What you see in the last plot is:
- All there clocks having about equal PN in the scart between 100-1kHz but taking into consideration that the DAM LRCK switches at a 1600 times higher frequency, a comparable PN figure need to recalculated - no? You treat and compare these objects as clocks - describing their PN - the you should also do what you do in other situations when the clocks have different frequency.
- DAM being hit by its clock adjustment but is probably also worse without the adjustments - we don't know. But its not letting anything through - it's creating its own mess. Different LRCK frequencies compared makes comparison hard?
- Above 1k, we see the DAM fifo working fine suppressing the RPIs higher frequency jitter. Different LRCK frequencies compared makes comparison hard?
This is to debunk your statement that the DAM passes through jitter. It doesn't above its f0 freq. This fact does not make it any better - it corrects a faulty technical analysis made by you. A fifo based on memory cant let anything through - if the clock is bad after the PLL, other technical resons must be searched for.
//
Sorry - yes you named the sources.
How does fiforpi and RPI in the last chart relate? Is it:
- AUNE X5S SD card player for S/PDIF - is this fiforpi?
- RPI 4 standalone source for I2S - is the RPI?
I don't question your listening impression (it not possible to deny a persons experience)
You see, there is a problem with the DAM DPLL that you may have heard about - it varies its clock every second or 10 seconds or 2 times a second so it is hard to do comparisons from different moment in time - 1 minute, 20 minutes... this can complicate comparisons - one would have to have both input and output PN measured at the same time to be sure what is compared.
What you see in the last plot is:
- All there clocks having about equal PN in the scart between 100-1kHz but taking into consideration that the DAM LRCK switches at a 1600 times higher frequency, a comparable PN figure need to recalculated - no? You treat and compare these objects as clocks - describing their PN - the you should also do what you do in other situations when the clocks have different frequency.
- DAM being hit by its clock adjustment but is probably also worse without the adjustments - we don't know. But its not letting anything through - it's creating its own mess. Different LRCK frequencies compared makes comparison hard?
- Above 1k, we see the DAM fifo working fine suppressing the RPIs higher frequency jitter. Different LRCK frequencies compared makes comparison hard?
This is to debunk your statement that the DAM passes through jitter. It doesn't above its f0 freq. This fact does not make it any better - it corrects a faulty technical analysis made by you. A fifo based on memory cant let anything through - if the clock is bad after the PLL, other technical resons must be searched for.
//
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Maybe I was not clear.
The 595s does not care about different frequencies, they don't take into account the 6dB/oct decrease in PN for each halving of the frequency, they are fed with that clock as is.
So the phase noise of the LRCK is exactly what was measured, the 6dB/oct decrease in PN is just theoretical, while the facts are very clear: the incoming LRCK from the RPI has a phase noise around -125dBc at 10Hz from the carrier, the phase noise of the LRCK coming out from the DAM1021 front end feeding the 595s is around -95dBc, so around 35dB worse than the incoming signal.
Is this clear?
Moreover I have published the phase noise of my cheap DDS signal generator measured at the same frequency of the LRCK coming out from the DAM1021 in the first 2 plots just for reference.
The phase noise of the LRCK coming out from the DAM1021 is around 20dB worse than the one measured with the RIGOL DG1022 DDS signal generator at the same frequency.
Is this clear?
The FifoPi was not part of the setup, I have published the curve just for reference, so you can compare the phase noise of the LRCK between the FifoPi and the DAM1021 both fed with the same source:
1) RPI standalone source --> FifoPi --> LRCK phase noise
2) RPI standalone source --> DAM1021 --> LRCK phase noise
With the same source the DAM1021 LRCK is 32dB worse than the LRCK of the FifoPi.
Again, maybe I was not clear or you have not understood how phase noise is measured.
Again, the phase noise is short term stability measurement, so the long term fluctuation does not affect the measurement.
There is no comparisons from different moment in time - 1 minute, 20 minutes and so on -, the TimePod acquires million of samples and makes the average, so the frequency adjustments you have pointed out don't affect the averaging, they are discarded.
If it was as you think I should see these fluctuations in the curve during the measurement since the TimePod updates the curve real time.
Nothing of this was plotted during the acquisition,
The development of the curve has always been linear without any alteration.
It's enough obvious, you are pointing out long term stability issues while phase noise measures the short term stability.
Again, I suggest Rubiola.org to understand what is phase noise.
"All there clocks having about equal PN in the scart between 100-1kHz but taking into consideration that the DAM LRCK switches at a 1600 times higher frequency, a comparable PN figure need to recalculated - no?"
NO! See above.
"Different LRCK frequencies compared makes comparison hard?"
NO! See above.
Above 1k from the carrier even the worst oscillator on the market performs at least -130dBc, what you have to look for is the close in phase noise.
At such that distance from the carrier (1K and upper) all the oscillators perform very similar, it's the close in phase noise that makes the difference between oscillators.
"Different LRCK frequencies compared makes comparison hard?"
Again NO! See above.
And finally you have a pair of issues in the DAM1021.
It tracks the incoming phase noise and reflects it to the output.
Indeed it's source dependent.
Again, take a look at the x48 family plot you see a difference around 12-13 dB between the S/PDIF and the I2S sources.
Different sources, different LRCK phase noise.
AGAIN, this has nothing to do with the frequency adjustments, they are long term stability issues while the phase noise is a short term stability indicator.
The DAC is not well isolated from the LRCK phase noise coming from the source.
The time domain of the FIFO is not well isolated from the time domain of the source.
Why do you think MSB Tech (and we're doing the same thing too) used fiber optics to totally isolate the DAC from the source?
In the DAM021 all signals are managed by the FPGA (and also by the micro), there is no isolation between the incoming and the output signals.
This get all the system prone to mix the time domains with reflections and beatings.
If the 2 time domains were really isolated you should not get any difference in the LRCK output phase noise.
The measured phase noise should be the same with whatever source, ie the phase noise of the FIFO buffer clock.
With the DAM1021 is not so, the second phase noise plot (3.072 MHz LRCK) clearly shows the difference.
The second issue is related to the poor quality of the master clock used (the Si514).
This means that even if the DAM1021 was not affected by the incoming phase noise you will get anyway a poor LRCK since it's derived from the poor master clock used.
You have not corrected any faulty technical analysis, your analysis is faulty.
"A fifo based on memory cant let anything through" only if the different time domains are well isolated, that's not happen in the DAM1021.
The 595s does not care about different frequencies, they don't take into account the 6dB/oct decrease in PN for each halving of the frequency, they are fed with that clock as is.
So the phase noise of the LRCK is exactly what was measured, the 6dB/oct decrease in PN is just theoretical, while the facts are very clear: the incoming LRCK from the RPI has a phase noise around -125dBc at 10Hz from the carrier, the phase noise of the LRCK coming out from the DAM1021 front end feeding the 595s is around -95dBc, so around 35dB worse than the incoming signal.
Is this clear?
Moreover I have published the phase noise of my cheap DDS signal generator measured at the same frequency of the LRCK coming out from the DAM1021 in the first 2 plots just for reference.
The phase noise of the LRCK coming out from the DAM1021 is around 20dB worse than the one measured with the RIGOL DG1022 DDS signal generator at the same frequency.
Is this clear?
The FifoPi was not part of the setup, I have published the curve just for reference, so you can compare the phase noise of the LRCK between the FifoPi and the DAM1021 both fed with the same source:
1) RPI standalone source --> FifoPi --> LRCK phase noise
2) RPI standalone source --> DAM1021 --> LRCK phase noise
With the same source the DAM1021 LRCK is 32dB worse than the LRCK of the FifoPi.
Again, maybe I was not clear or you have not understood how phase noise is measured.
Again, the phase noise is short term stability measurement, so the long term fluctuation does not affect the measurement.
There is no comparisons from different moment in time - 1 minute, 20 minutes and so on -, the TimePod acquires million of samples and makes the average, so the frequency adjustments you have pointed out don't affect the averaging, they are discarded.
If it was as you think I should see these fluctuations in the curve during the measurement since the TimePod updates the curve real time.
Nothing of this was plotted during the acquisition,
The development of the curve has always been linear without any alteration.
It's enough obvious, you are pointing out long term stability issues while phase noise measures the short term stability.
Again, I suggest Rubiola.org to understand what is phase noise.
"All there clocks having about equal PN in the scart between 100-1kHz but taking into consideration that the DAM LRCK switches at a 1600 times higher frequency, a comparable PN figure need to recalculated - no?"
NO! See above.
"Different LRCK frequencies compared makes comparison hard?"
NO! See above.
Above 1k from the carrier even the worst oscillator on the market performs at least -130dBc, what you have to look for is the close in phase noise.
At such that distance from the carrier (1K and upper) all the oscillators perform very similar, it's the close in phase noise that makes the difference between oscillators.
"Different LRCK frequencies compared makes comparison hard?"
Again NO! See above.
And finally you have a pair of issues in the DAM1021.
It tracks the incoming phase noise and reflects it to the output.
Indeed it's source dependent.
Again, take a look at the x48 family plot you see a difference around 12-13 dB between the S/PDIF and the I2S sources.
Different sources, different LRCK phase noise.
AGAIN, this has nothing to do with the frequency adjustments, they are long term stability issues while the phase noise is a short term stability indicator.
The DAC is not well isolated from the LRCK phase noise coming from the source.
The time domain of the FIFO is not well isolated from the time domain of the source.
Why do you think MSB Tech (and we're doing the same thing too) used fiber optics to totally isolate the DAC from the source?
In the DAM021 all signals are managed by the FPGA (and also by the micro), there is no isolation between the incoming and the output signals.
This get all the system prone to mix the time domains with reflections and beatings.
If the 2 time domains were really isolated you should not get any difference in the LRCK output phase noise.
The measured phase noise should be the same with whatever source, ie the phase noise of the FIFO buffer clock.
With the DAM1021 is not so, the second phase noise plot (3.072 MHz LRCK) clearly shows the difference.
The second issue is related to the poor quality of the master clock used (the Si514).
This means that even if the DAM1021 was not affected by the incoming phase noise you will get anyway a poor LRCK since it's derived from the poor master clock used.
You have not corrected any faulty technical analysis, your analysis is faulty.
"A fifo based on memory cant let anything through" only if the different time domains are well isolated, that's not happen in the DAM1021.
Here is now again how you typically mix up the discussion - starting to argue about the LRCK at the 595s and how they effect it - totally irrelevant for the discussing about the different clocks performance and how you compare them.
You shouldn't "scale" the DAM LRCK down, you should recalculate the other ones upwards.
Why mix in the Rigol clock - completely irrelevant. Just confuses things.
"Moreover the phase noise is short term stability measurement, so the long term fluctuation does not affect the phase noise."
Will it exclude wander? Under what frequency?
"However the third plot clearly prove that the DAM is source dependent since there is 12-13 dB of phase noise difference betwen the different sources."
No, I argue that you see the Si performance when constantly changed - i.e. the wander due to the DPLL. You don't have the input to do that statement because you dont have a plot of the Si standing still.
//
You shouldn't "scale" the DAM LRCK down, you should recalculate the other ones upwards.
Why mix in the Rigol clock - completely irrelevant. Just confuses things.
"Moreover the phase noise is short term stability measurement, so the long term fluctuation does not affect the phase noise."
Will it exclude wander? Under what frequency?
"However the third plot clearly prove that the DAM is source dependent since there is 12-13 dB of phase noise difference betwen the different sources."
No, I argue that you see the Si performance when constantly changed - i.e. the wander due to the DPLL. You don't have the input to do that statement because you dont have a plot of the Si standing still.
//
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No mix up, the only thing that does really matter is the LRCK phase noise, the frequency does not matter.
I have not measured the Si514 phase noise, there is the datasheet for it, just take a look at the datasheet.
No needs of mesurement, the datasheet clearly shows it's a poor oscillator, far worse than the Crystek that's already a crappy oscillator.
Can you understand I have measured the phase noise of the LRCK output from the DAM1021 ??????
Can you understand that for such kind of DAC the LRCK is the only crucial signal????
Can you understand that ladder of the DAM1021 is updated by the LRCK clock????
Can you then understand that the phase noise of the LRCK is the only one that affects the digital to analog conversion????
Can you understand that the phase noise is an absolute value so there is nothing to scale?????
Can you understand that running the LRCK at these high frequency is a design and operating choice????
I don't believe so.
Please take a look at the schematic I have published, and again take your time to study all the papers you can find on Rubiola.org.
The Rigol phase noise is a reference measured at the same frequency of the LRCK, so you have nothing to scale.
Can you understand that the phase noise of the LRCK measured at the output of the DAM1021 is far worse than the one measured at the output of a cheap chinese DDS signal generator?
This is the reason I have published the Rigol phase noise plots.
Can you realize anything from the comparison?
"Will it exclude wander? Under what frequency?"
YES, I have already explained the reasons in the previous post.
I can't explain better, sorry.
Again, please just study Rubiola.org to better understand, or just buy a Timepod and try yourself.
It looks like you have difficult to read a phase noise plot.
"but you never presented any measurement of them".
Again, look at the third plot, you can find the phase noise of both the RPI (the source) and the DAM.
Are you able to compare them?
The LRCK phase noise is degraded by 35 dB from the input to the output of the DAM1021.
Then apply this to the schematic I have published and draw your own conclusion.
Have you ever wondered why the designer never replied to your requests to modify the frequency adjustment operated by the PLL?
I have not measured the Si514 phase noise, there is the datasheet for it, just take a look at the datasheet.
No needs of mesurement, the datasheet clearly shows it's a poor oscillator, far worse than the Crystek that's already a crappy oscillator.
Can you understand I have measured the phase noise of the LRCK output from the DAM1021 ??????
Can you understand that for such kind of DAC the LRCK is the only crucial signal????
Can you understand that ladder of the DAM1021 is updated by the LRCK clock????
Can you then understand that the phase noise of the LRCK is the only one that affects the digital to analog conversion????
Can you understand that the phase noise is an absolute value so there is nothing to scale?????
Can you understand that running the LRCK at these high frequency is a design and operating choice????
I don't believe so.
Please take a look at the schematic I have published, and again take your time to study all the papers you can find on Rubiola.org.
The Rigol phase noise is a reference measured at the same frequency of the LRCK, so you have nothing to scale.
Can you understand that the phase noise of the LRCK measured at the output of the DAM1021 is far worse than the one measured at the output of a cheap chinese DDS signal generator?
This is the reason I have published the Rigol phase noise plots.
Can you realize anything from the comparison?
"Will it exclude wander? Under what frequency?"
YES, I have already explained the reasons in the previous post.
I can't explain better, sorry.
Again, please just study Rubiola.org to better understand, or just buy a Timepod and try yourself.
It looks like you have difficult to read a phase noise plot.
"but you never presented any measurement of them".
Again, look at the third plot, you can find the phase noise of both the RPI (the source) and the DAM.
Are you able to compare them?
The LRCK phase noise is degraded by 35 dB from the input to the output of the DAM1021.
Then apply this to the schematic I have published and draw your own conclusion.
Have you ever wondered why the designer never replied to your requests to modify the frequency adjustment operated by the PLL?
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That's a bit short-sighted !
I have a DAM1021 V1 heavily modded,
my friend has an AYA TDA1541 DAC modded and a DAM1021 v3 stock.
On the last listening session we had, my DAM1021 V1 was the best sounding: natural, not aggressive, detailed, depth soundstage,...
Unmodded my DAM1021 V1 was really not good, the AYA DAC was much better, no contest then, but that was 5 years ago.
Now my modded DAM1021 has surpassed the AYA Dac.
The only thing that I haven't changed on my DAM1021 is the clock,
although the existing clock is much better decoupled.
Mods on my DAM1021 V1:
- external shunt PS
- all onboard regulators(4) replaced with muzgdiy regs
- vref BC550/560 transistor mod
- extra capacitance to the vrefs and clock (c0g ceramics)
- Amanero has its own low noise PS
There is no way to change the master clock of the DAM1021, it only works with SiLabs oscillators since they have their own protocol to manage the PLL.
I'm happy for you if you like your modded DAM1021.
I prefer to design my own FIFO and DAC since I don't agree with any of the DAM's design choices, so I see no reason to upgrade it other than to completely replace the front end.
Do the DAM fifo/PLL let jitter through?
It is the only question I have been debating with you the last week. You however, have been mixing up 2-3 topics all the time - must be confusing for you - it is for me.
//
I think I have already replied one million times.
Yes, the jitter of the source passes through the DAM FIFO/PLL, it's clearly visible in the second plot.
Two different incoming clock, 13 dB phase noise difference at the output (1Hz up to 1kHz from the carrier).
If the time domains were really isolated you should get the same phase noise at the output, the one of the master clock of the DAM.
With the DAM1021 it's not so, THE TIME DOMAINS ARE NOT WELL ISOLATED, so the jitter from the source affects the output.
This is the first issue I have mentioned in the previous post.
Don't ask me why this happen, ask the designer.
I cannot access schematic and firmware so I cannot find the issue, I can only assume the time domains are mixed up in the FPGA and in the micro.
I have said infinite times that it's not the proper way to isolate the time domains.
And please stop addressing the issue to the long term stability until you have finished studying the Rubiola's papers and you have understood that the long term stability does not affect the phase noise.
Then there is the second issue I mentioned.
Not only the jitter of the source is reflected to the output but the master clock of the DAM1021 degrades the incoming clock by 35 dB as clearly visible in the third plot.
Summarizing the clock from the DAM1021 is 35dB worse than the clock of the RPI and 20dB worse than a cheap DDS signal generator.
That's all.
Again:
Have you ever wondered why the designer never replied to your requests to modify the frequency adjustment operated by the PLL?
Yes, the jitter of the source passes through the DAM FIFO/PLL, it's clearly visible in the second plot.
Two different incoming clock, 13 dB phase noise difference at the output (1Hz up to 1kHz from the carrier).
If the time domains were really isolated you should get the same phase noise at the output, the one of the master clock of the DAM.
With the DAM1021 it's not so, THE TIME DOMAINS ARE NOT WELL ISOLATED, so the jitter from the source affects the output.
This is the first issue I have mentioned in the previous post.
Don't ask me why this happen, ask the designer.
I cannot access schematic and firmware so I cannot find the issue, I can only assume the time domains are mixed up in the FPGA and in the micro.
I have said infinite times that it's not the proper way to isolate the time domains.
And please stop addressing the issue to the long term stability until you have finished studying the Rubiola's papers and you have understood that the long term stability does not affect the phase noise.
Then there is the second issue I mentioned.
Not only the jitter of the source is reflected to the output but the master clock of the DAM1021 degrades the incoming clock by 35 dB as clearly visible in the third plot.
Summarizing the clock from the DAM1021 is 35dB worse than the clock of the RPI and 20dB worse than a cheap DDS signal generator.
That's all.
Again:
Have you ever wondered why the designer never replied to your requests to modify the frequency adjustment operated by the PLL?
You're missing the point, I know that you can't change the master clock.
I've upgraded everything besides the front end, now it plays better than a very good TDA1541.
So it's not only the front end that can be changed to achieve a better sound quality.
It's always a summon of it all.
By only focusing on the front end it's possible that you don't achieve a better sound quality because the limiting factor is somewhere else.
Regardless of your subjective impressions that are and remain subjective, the limiting factor is not somewhere else.
I have published the schematic of the DAC part of the DAM1021, if you have the skill to read it you see that the DAC part is very simple, 595s and resistors ladder, nothing more.
So what remains?
Just the front end.
Forget the power supply, it cannot cures the poor SI oscillator and the not well isolated architecture of the front end, it can only make things worse.
Have you an idea of what "different time domains" means?
If so you can understand where the issue lies.
Andrea does absolutely the only right thing - no matter for which reason: To bring the real potential of the DAM to light. The only thing that's not clear to me is what happens next....
I mean, volume control can be done pretty perfectly in analog domain. Even if there are few, if any, known solutions of it. But what if the DAM sounds without a filter? I miss in Andrea's philosophy (even of his own DAC) a plausible hint how the "shrill" tones of a pure NOS DAC should be handled. Regardless of the positive portions of NOS. Previous upsampling does not apply. This is a clear OS solution. Better a practical OS approach then.... At the moment, the experiments with the DAM filters are very promising here.
I mean, volume control can be done pretty perfectly in analog domain. Even if there are few, if any, known solutions of it. But what if the DAM sounds without a filter? I miss in Andrea's philosophy (even of his own DAC) a plausible hint how the "shrill" tones of a pure NOS DAC should be handled. Regardless of the positive portions of NOS. Previous upsampling does not apply. This is a clear OS solution. Better a practical OS approach then.... At the moment, the experiments with the DAM filters are very promising here.
You see worse clock but you don't know what cause the degradation - I think you need to agree on that. Your position is possible but it is not proven by your measurements.
Its is not just a long term stability like a poor crystal but there are changes that makes the Si clock go crazy up to 2 times a second - don't you think that adds to the characteristics?
It doesn't make any difference how many times you repeat a faulty assumption - it doesn't come true anyway. A 4 sample fifo followed by a DPPL with 0,5 second time constant block jitter above 2 Hz.
Maybe you should focus on how the jitter of the incoming clock that is much better than the internal clock can decrease the performance of the internal clock by 35 dB. (How do you even know the performance of the internal clock?) Please describe the electrical "chain of events" that makes this happen.
Take this statement: "Not only the jitter of the source is reflected to the output but the master clock of the DAM1021 degrades the incoming clock by 35 dB as clearly visible in the third plot."
Can you separate whet is "reflected" and what is "degradation"?
I mean I agree on the degradation in the sense that the incoming clock is replaced by a much worse clock - this is not what I am debating - but rather the "jitter of the source is reflected to the output". How do you tell by your measurement that the "jitter of the source is reflected to the output"?
This is where your logic goes wrong - you don't know what the DAM LRCK jitter is composed of. At the point of the 595s, everything before that becomes a black box - with your way of measuring.
To prove what you state you need to change the incoming jitter from very bad to very good, measure that and at the same time, measure how the jitter vary at the 595s. When I see that, I believe your claim that jitter is passed through above the f0 of the DPLL.
But as you state yourself - the intrinsic jitter of the Si is so much higher than the incoming clock that it is completely drowned by the Si so I don't see how you can identify what comes from where...
I wish you can stay on the question at hand and not mix in a lot of other stuff all the time in your answers.
//
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Unfortunately there is a price to pay.
We have deliberately chosen to make the DACs work at lower frequencies because this allows us to use lower frequency oscillators with better phase noise and to avoid the use of a PLL, which is usually deleterious in audio.
So the max sample rate will be 384 kHz with our DACs and also with the upgraded DAM1021 (with 22/24 MHz oscillators).
So if one would oversampling the job should be done in software before feeding the FIFO Lite.
I think that is exactly the point - perhaps one of the few that the DAM has ahead: It allows a concrete solution to the problem plus the freedom of one's own decision. No one will want to have a DAC that is perfect in many ways, but doesn't want to listen to music with antique tweeters whose rise time is so bad that you simply can't hear the problem.
Well, I have measured a difference of 13 dB with two different sources.
Then do you believe the time domains are well isolated?
If so I think we can stop here, you don't realize what different time domains means so the debating is useless.
But if you agree on that, where this phase noise difference come from?
I assume from the source simply because is the only thing I have changed in the comparison.
And what does it mean?
It does mean that the FIFO does not work properly, ie the FIFO does not isolate the DAC from the source.
Something passes through.
You think it depend on the frequency adjustment and I repeat it cannot affect the short term stability.
Maybe also the designer thinks the same, since he has never replied to your requests to modify the frequency adjustment operated by the PLL.
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I usually listen to music with AMT tweeters which are the fastest tweeters available (corona plasma apart), I have just a pair of Great Heil to install in my reference speakers.
I have never felt the problem you are pointing out.
The system I have built for a friend plays redbooks only without oversampling with the TDA1541A DAC, and the speakers use ribbon tweeters.
The sound is pretty detailed and never harsh and aggressive, exactly the opposite you are pointing out.
Maybe your problem lies in the electronics if you are using solid state amplifier with massive feedback.
But this is off topic, there are plenty of threads about this.
Then you would say our DACs phylosophy is is outdated for the market?
It could be, but we don't care about the market.
The market is the target of Soeren not our goal.
We are hobbyist who want to build the best audio system as possible for ourselves, we care less than zero about the market.