Thanks for the tutorials 😀
I've found a KiCAD import video on the ultra librarian which shows things clearly and I understand by now that I need a different file (symbol.lib) which I don't have. I'll try to get it from the ultra librarian despite the fact that it now wants me to register, what it did not do on my former try...
Well, I'll be back...
Winfried
PS: Going through the TI websites loads the files from ultra librarian without registration! 😛 😀
I've found a KiCAD import video on the ultra librarian which shows things clearly and I understand by now that I need a different file (symbol.lib) which I don't have. I'll try to get it from the ultra librarian despite the fact that it now wants me to register, what it did not do on my former try...
Well, I'll be back...
Winfried
PS: Going through the TI websites loads the files from ultra librarian without registration! 😛 😀
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Winfried, KiCad sure has a competent library editor, that is, it should be not a hell of work to copy a symbol (single op 8 pin), modifiy it and then use it, linking the pins to the standard SO-8 pads (which is available). Pretty much like in any other CAD software. I'm not famliar with KiCad, though.
Being able to create your own symbols, fooprints and libraries is one of the task you'll have to master sooner or later anyway. Pre-made libraries are convenient, of course, but before I'd go to tons of tries with imports after websearch for libs I'd rather try create what is need, using copy/paste/modify mainly.
Being able to create your own symbols, fooprints and libraries is one of the task you'll have to master sooner or later anyway. Pre-made libraries are convenient, of course, but before I'd go to tons of tries with imports after websearch for libs I'd rather try create what is need, using copy/paste/modify mainly.
In fact for some parts I prefer to make my own. i'm fairly competent with autocad/illustrator for making custom pads; having used such spline based tools for more than 30 years in other capacities. sometimes I will integrate a part into a copper pour by making a custom part, or construct a part that has built in pads for small bypass caps directly on the pins. That way I also dont get the app complaining about clearance errors at check time .
It's all OK folks,
sorry for sharing my frustration 😉, you're all right, editing footprints is not rocket science, yes, OK 🙂
As hinted at, the OPA1632 footprint is now imported, was straight forward with the KiCAD instructions from the download website. Next step is to enter the schematic, potentially I will edit the 1632' schematic footprint and then I'll go from there trying out the 4-layer PCB.
It seems to me like a big bunch of vias will be "inherent" to the PCB when using a GND layer, a V+/V- layer and two signal layers. Would it be viable to have
Signals: Cu Layer 1 and 2
GND: Cu Layer 3
V+/V-: Cu Layer 4
or what would be the "right" layering?
I'll be back.
Winfried
sorry for sharing my frustration 😉, you're all right, editing footprints is not rocket science, yes, OK 🙂
As hinted at, the OPA1632 footprint is now imported, was straight forward with the KiCAD instructions from the download website. Next step is to enter the schematic, potentially I will edit the 1632' schematic footprint and then I'll go from there trying out the 4-layer PCB.
It seems to me like a big bunch of vias will be "inherent" to the PCB when using a GND layer, a V+/V- layer and two signal layers. Would it be viable to have
Signals: Cu Layer 1 and 2
GND: Cu Layer 3
V+/V-: Cu Layer 4
or what would be the "right" layering?
I'll be back.
Winfried
I wonder why it doesn't match at all with the simple loop cutting model. When the open-loop input impedance of the LT1468 is high enough and the open-loop output impedance low enough, you can calculate the loop gain by just cutting the loop at the op-amp output, forcing an AC voltage at the node that connects R1, C1 and R3, and calculate what AC voltage that will cause at the op-amp output. (Measuring or simulating it that way can lead to complications with keeping the bias point as it's supposed to be, but that's no issue for calculations.)
For frequencies high enough for C1 and C3 to have a lower impedance than R3 and R2, the result is one quarter of the open-loop gain when you use 220 pF and 660 pF, and 1/41 times the open-loop gain when you use 500 pF and 20 nF. It's just the capacitive voltage division times the open-loop gain of the op-amp.
So all in all, there should be about 20 dB difference in loop gain at high frequencies according to the loop cutting model. As R2 C3 = 30 us in the 500 pF and 20 nF case, the loop gain plots should start differing from each other from about 1/(2 pi 30 us) ~= 5 kHz onward.
Marcel, interesting technical discussion, but most likely rather outside the intended goal of the OP.
So, If you want we could continue by using PM's, just an idea ?
Hans
Winfried, I would always prefer to have the signal traces "in sight", and with such a simple circuit diagram it should be (almost) possible to get all the signals on one layer. When this seems not possible I would use the bottom layer as second signal layer, also enabling to mount components on the backside.
And leave the inner layers for Gnd and Supply.
When experimenting, you will never have the problem of buried signal traces.
That would be my approach.
Hans
Winfried, I'd suggest the stackup as shown in my post, pretty much similar to what Hans is saying.
Don't try to increase density to the max, or if so, at least use 0805's to start with.
And no vias in pads ;-)
- Top : Components, Signals, and GND plane as much as possible
- 2 : GND plane, no signals except for short signal bridging
- 3 : Supply Plane, and the occasional auxiliary signal
- Bottom : Supply Plane, and the occasional auxiliary signal (and maybe components)
Don't try to increase density to the max, or if so, at least use 0805's to start with.
And no vias in pads ;-)
Parting comment from my side: With 10nF + 2*500pF you've increased the differential feedback factor (1/ß) which now has a long rising slope towards HF until it flats out when caps start to dominate noise gain. This intersects with the falling slope of the open-loop gain Aol --> a recipe for potential disaster when the flat part has not been establish long enough before it intercepts with the Aol... https://www.ti.com/lit/an/sboa015/sboa015.pdf, Figs. 5 and 6. The hump in the Acl of Fig. 6 is btw what I see when I model that I/V with standard single-pole idealized opamp with ~10MHz GBW
unless you want to pay extra for vias in pads 🙂 I prefer via in pad myself if I can justify its existence.
If you cant do via in pad, place the vias like so, ignore the layout, routing is incomplete, my example is the vias on C1, use minimum of 2 and if 2, place by the side and as close to the center as possible. this minimises inductance.
Thx for the many valuable tips on PCB creation and design tools. Also impressed by the calculation module that Kicad supplies.
Hans
Hans
No problem at all @Hans Polak. I have witnessed many threads here, as well as this one, where you give generously of your time and knowledge. I'm glad to be able to give some back.
I'll definitely have to give Kicad a good look now with the new version; ive been impressed with it before. A dedicated inbuilt maths module is for sure a winning feature and is one of the things that makes Altium so powerful. That a free open-source package is able to get even part way there is amazing!
I'll definitely have to give Kicad a good look now with the new version; ive been impressed with it before. A dedicated inbuilt maths module is for sure a winning feature and is one of the things that makes Altium so powerful. That a free open-source package is able to get even part way there is amazing!
Yeah, one of the features I came to like with Altium as well (as much as I hate in other aspects). And things like Paste Special/Array for large BGA's and LQFPs etc.
But I will never understand why land patterns in spec sheets are not dimensioned as centroids + size(shape), that would make life so much easier. I mean, for how long are we using CAD systems which have always used that metric?
yeah I can only speak with respect to my short time with Altium designer demo and being a long time fan of Robert Feranec's wonderful youtube channel. I dont own a license yet. It has never been a value proposition, given my usage. Its handling of large BGAs and HDI layout in general. appears to be a major strength. Your suggestion for being able to quickly define land patterns by center+dimension, as one would in autocad etc, is a very reasonable one.
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Hi folks,
maybe someone ist interested in little update...
I've tried KiCAD 6.0.... This program is just beyond me, overburdened with features, non-intuitive, takes ages to even get a schematic done, it drove me "nuts". KiCAD may be well usable for CAD experts, but is NO SW for me! Uninstalled...
DipTrace (private use edition) is a very different animal: A step-by-step tutorial got me started on schematic editing and nice video greatly helped to insert the OPA1632 into the libraries for schematic, layout and 3D visualisation. Editing the 1632 schematic footprint to my liking was nicely intuitive, as was the schematic entry and editing. The node and wire connection concept were understood quickly. A fast learning curve to achieve a nice looking schematic was possible even for me as beginner.
Next I'll give the four layer, schematic based, board layouting a go. Hopefully this will be as intuitively doable as the schematic. We'll see...
I'll be back.
Greetings,
Winfried
maybe someone ist interested in little update...
I've tried KiCAD 6.0.... This program is just beyond me, overburdened with features, non-intuitive, takes ages to even get a schematic done, it drove me "nuts". KiCAD may be well usable for CAD experts, but is NO SW for me! Uninstalled...
DipTrace (private use edition) is a very different animal: A step-by-step tutorial got me started on schematic editing and nice video greatly helped to insert the OPA1632 into the libraries for schematic, layout and 3D visualisation. Editing the 1632 schematic footprint to my liking was nicely intuitive, as was the schematic entry and editing. The node and wire connection concept were understood quickly. A fast learning curve to achieve a nice looking schematic was possible even for me as beginner.
Next I'll give the four layer, schematic based, board layouting a go. Hopefully this will be as intuitively doable as the schematic. We'll see...
I'll be back.
Greetings,
Winfried
Yes, having had another play with kiCAD last night, id have to agree the layout is not the most intuitive if you dont know what you are looking at. Diptrace has its quirks and isnt as powerful, but its pretty easy to learn.
OK, yes friends, I've had my fun playing with DipTrace... Entered the schematic, learned how to work with the net (I thought...). Then I ran the electrical rule check before going for the board layouting, seemingly just for "fun" to verify my "nice" work result. Well, a "plethora" of connection error messages was the result and looking closely, I was unable to easily see what the issues were. So, that's how that went so far...
Out of that frustration (or better: experience) I did not try the 4-layer thing (yet). But since I had my 2-layer layout done, I took another thorough look at that and it appeared to me: Hell! All component connectivity nicely fits on the top layer without vias! "Just" the supply voltages (i.e. 2x V+ wires and 2x V- wires) for the 2 OPA chips had via connections and cut the GND plane apart. Ha! I don't need four layers but 3 suffice! The third layer could be on the back side below the GND Plane: This third layer is now made of 4 straight, soldered isolated thin wire-bridges from the V+/- input caps directly to the IC pins.
Another step forward is, that I have designed the final board to contain all six balanced buffer stages needed. Every Stereo pair has its own V+/- supply connection & buffer RC, the GND connection is one common wire to the central star-ground. This results in a 120x65mm 2-layer board with 5 monting holes to "piggy back" the balanced bufferboard on the existing main board. the bufferboard is screw-fastened on five ~10mm high plastic poles which get "glued" on free spaces of the main board by double sided adhesive tape snippits.
Here's an impression of the board and the slightly updated (one channel) schematic:
Please don't kill me for not taking the 4-layer recommendation! 😉
Regards,
Winfried
Out of that frustration (or better: experience) I did not try the 4-layer thing (yet). But since I had my 2-layer layout done, I took another thorough look at that and it appeared to me: Hell! All component connectivity nicely fits on the top layer without vias! "Just" the supply voltages (i.e. 2x V+ wires and 2x V- wires) for the 2 OPA chips had via connections and cut the GND plane apart. Ha! I don't need four layers but 3 suffice! The third layer could be on the back side below the GND Plane: This third layer is now made of 4 straight, soldered isolated thin wire-bridges from the V+/- input caps directly to the IC pins.
Another step forward is, that I have designed the final board to contain all six balanced buffer stages needed. Every Stereo pair has its own V+/- supply connection & buffer RC, the GND connection is one common wire to the central star-ground. This results in a 120x65mm 2-layer board with 5 monting holes to "piggy back" the balanced bufferboard on the existing main board. the bufferboard is screw-fastened on five ~10mm high plastic poles which get "glued" on free spaces of the main board by double sided adhesive tape snippits.
Here's an impression of the board and the slightly updated (one channel) schematic:
Please don't kill me for not taking the 4-layer recommendation! 😉
Regards,
Winfried
