First Watt SIT5

as posted before Christmas... a compound transistor?
That implies a combination of a 'feedback' from the drain to the gate through the driver mosfet, maybe both sides - or just on the SIT side. Or only on the other side. Anyway . . . somewhat less simple.
 

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My guess: The Mosfet is connected through a resistor divider network to SIT and Output. Make this resistors ratio 1 : 5 and the Mosfet voltage contribution to the output should be five times less than that of the SIT. That is 20%…
That was before coffee... The ratio would have been 1:4, but now I am doubting myself.

Both SIT source and MOSFET source produce output. No voltage gain, in phase, source follower mode. The two devices share their source resistor.

The additional RC between MOSFET source and Output adds impedance, making the Mosfet contribute less. Does it also allow the shared source resistor to correct errors? The circuit reminds me of feedforward cancellation. But that is normally used for identical devices, and here they are quite different. This is no feedback either as the output is not fed back to an input.

Pa is making us think...
 
As you say, the network adjusts the ratio of the contributions of SIT and Mosfet.

The other more obscure part of the trick - imagine that the resistor in series with the
cap is zero, where the AC contributions approach 50/50.

Stan Ricker of JBL fame was a big fan of running his electrolytics back-to-back in series
with a charge applied between them so as to have them work push-pull AC with a DC
bias. This to reduce the distortion and also cancel the 2nd harmonic which would be the
dominant distortion.

In the diagram below, the output coupling caps have a DC bias and each carries the
bulk of the AC from their attached Fet, but in reverse phase. In this manner the 2nd
harmonic each would have is cancelled.

Also, the DC behavior of the Fets is governed by the resistor which degenerates and
stabilizes the DC bias while the AC behavior is undegenerated, allowing a wider Class A
operating region and better square law cancellation.

If you are operating push-pull followers with a single polarity supply this circuit has
something to offer, independent of the control of output ratios.
 

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This is the nicest one up to now!

I chose the Mosfet source resistor for equal contribution, thanks Nelson for explanation to this point, value is about 1R but must be outside the two caps point.

and second the biasing mechanism ZM found some time ago for DEFiSIT, see here

works like glue!

Having both contributions on same level, I inserted the 2R in the lower cap from Mosfet and it has now around 20%.
Current might be a bit low, how many do I need for 35W with 60V rail?

Happy thanks to Nelson and ZM!
 

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R2 in you case is not bypassed so
Also, the DC behavior of the Fets is governed by the resistor which degenerates and
stabilizes the DC bias while the AC behavior is undegenerated, allowing a wider Class A
The ac part of the above sence is not true in your case because you don’t have r2 bypassed.
Try including the 2r resistor inside the loop and use 10r for the other resistor, see what you get.
 
as posted before Christmas... a compound transistor?
That implies a combination of a 'feedback' from the drain to the gate through the driver mosfet, maybe both sides - or just on the SIT side. Or only on the other side. Anyway . . . somewhat less simple.
Ha, I misread as often. But that is imagination.
ThePass: The interesting thing is the complementary circuit which biases the output SIT.