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There was some talk of a higher powered sim F7. Would it be as easy as paralleling more matched laterals and raising the voltage, with in reason or jfet SOA, to get more power?
PCF resistor values will change.
I just used a trimpot and dialed it in while watching the output impedance.
I just used a trimpot and dialed it in while watching the output impedance.
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You watched the output impedance and calculated the dampening factor you are trying to achieve?
In my brain.
My brain is a Mk1 Damping factor calculator. Hahaha.
I meant indirectly, ie watch the signal amplitude increase and then determine your output impedance through calculation.
What are the chances both N & P laterals run at the same temperature?
What if the N-ch runs 5 degrees C higher?
The N & P ch are not matched.
All else being fine: bias and offset.
What if the N-ch runs 5 degrees C higher?
The N & P ch are not matched.
All else being fine: bias and offset.
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They are not far from their zero temp coefficient, so temperature variation
effects between the parts are minimized. Temperature stability and low
capacitance are the attractions of laterals. Low transconductance is the
downside.
effects between the parts are minimized. Temperature stability and low
capacitance are the attractions of laterals. Low transconductance is the
downside.
If bias and dc offset are correct then check thermal pads, heatsink surface, mounting bolt torque, etc.
Also check powersupply voltages, are equal ie Vds of each mosfet is the same.
Also check powersupply voltages, are equal ie Vds of each mosfet is the same.
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