If you are using the drawings to measure something during your build, I will recommend using one of these drawings (letter and a4):
http://viller.eu/audio/2009jan_gbf5/f5_letter.frontassembly.pdf
http://viller.eu/audio/2009jan_gbf5/f5_a4.frontassembly.pdf
http://viller.eu/audio/2009jan_gbf5/f5_letter.frontassembly.pdf
http://viller.eu/audio/2009jan_gbf5/f5_a4.frontassembly.pdf
Thanks.
Do you happen to have anything with dimensions on it? I'm going to transfer it right to a cad drawing.
Do you happen to have anything with dimensions on it? I'm going to transfer it right to a cad drawing.
Has anyone come across an illuminated switch for the F5 with 2 led outputs?
I was hoping I could find a switch that would allow me to light up 2 sides of it, independently from the power. I'd just connect the led outputs from the output boards to each side of the switch (instead of drilling out additional holes for them on the front panel of the chassis).
I was hoping I could find a switch that would allow me to light up 2 sides of it, independently from the power. I'd just connect the led outputs from the output boards to each side of the switch (instead of drilling out additional holes for them on the front panel of the chassis).
I've just finished building first channel of my F5. During the test phase I observed the following:
1. It tends to oscillate (about 1MHz) with high capacitive load even if no input signal is provided (0.33uF used and input shorten to the ground).
2. It tends to oscillate with square input signal with fast rise/fall times (100ns, 4Vpp input signal) . As well with such sharp square signal it gets significant overshoot if 2Vpp signal is given for example.
So, to solve these problems I've added 150pF capacitor from JFET gates to the ground.
No overshooting and oscillations and the bandwidth did not reduce for listening purposes.
Adding more values in gate-stoppers did not help at all.
Any comments?
1. It tends to oscillate (about 1MHz) with high capacitive load even if no input signal is provided (0.33uF used and input shorten to the ground).
2. It tends to oscillate with square input signal with fast rise/fall times (100ns, 4Vpp input signal) . As well with such sharp square signal it gets significant overshoot if 2Vpp signal is given for example.
So, to solve these problems I've added 150pF capacitor from JFET gates to the ground.
No overshooting and oscillations and the bandwidth did not reduce for listening purposes.
Adding more values in gate-stoppers did not help at all.
Any comments?
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I think it's public knowledge that you don't hook a capacitor
directly across the F5 outputs.
If you wish to tame your square wave response and you are
willing to introduce a capacitor to the circuit, the best place
is across the 50 ohm (two parallel 100 ohm) feedback resistors.
😎
directly across the F5 outputs.
If you wish to tame your square wave response and you are
willing to introduce a capacitor to the circuit, the best place
is across the 50 ohm (two parallel 100 ohm) feedback resistors.
😎
Thank you, Mr. Pass.
But my second test (an oscillation and overshooting with fast rise/fall square signal - 1kHz, 100ns edges) was done w/o any capacitive load (only 8Ohm resistor).
You said that adding a few pF capacitor to JFET gates would solve the overshooting issues, but it looks like it was not enough (typical JFET input capacitance is about 100pF at zero Vgs).
But my second test (an oscillation and overshooting with fast rise/fall square signal - 1kHz, 100ns edges) was done w/o any capacitive load (only 8Ohm resistor).
You said that adding a few pF capacitor to JFET gates would solve the overshooting issues, but it looks like it was not enough (typical JFET input capacitance is about 100pF at zero Vgs).
Last edited:
Thank you, Mr. Pass.
But my second test (an oscillation and overshooting with fast rise/fall square signal - 1kHz, 100ns edges) was done w/o any capacitive load (only 8Ohm resistor).
You said that adding a few pF capacitor to JFET gates would solve the overshooting issues, but it looks like it was not enough (typical JFET input capacitance is about 100pF at zero Vgs).
As a cure for oscillation problems, you could also add some series resistance with the gates of the jfets - Q1/Q2 - (100 to 221 R for example) and try to get higher resistor values for R13 - R14 (maybe 100 / 221 and perhaps as high as 1k, with tradeoff regarding absolute bandwidth) 🙂
Hope this helps 😎
nAr
nAr,
I'll try JFET gate resistors on my second channel. Increasing R13-R14 (330Ohm) value did not help at all.
Looks like the source of oscillation is JFETs, not MOSFETs. The oscillation happened only with high level square signal with sharp edges.
Anyway, adding 150pF capacitor to JFET gates cured the problem.
bobodioulasso,
I have no decouping electrolytics on the board rails.
Thank you, guys.
I'll try JFET gate resistors on my second channel. Increasing R13-R14 (330Ohm) value did not help at all.
Looks like the source of oscillation is JFETs, not MOSFETs. The oscillation happened only with high level square signal with sharp edges.
Anyway, adding 150pF capacitor to JFET gates cured the problem.
bobodioulasso,
I have no decouping electrolytics on the board rails.
Thank you, guys.
Last edited:
nAr,
adding 150pF capacitor to JFET gates cured the problem.
Just curious, was cap from gate to ground?
I've seen a few F5 builds where the power mosfets are mounted to the heatsinks, and the boards to the bottom panel. The thermistor is no where near the mosfets.
That's not a good idea I guess.
That's not a good idea I guess.
I didn't bother using thermistors for the biasing.
One less thing that can go wrong.
I didn't use current limiting either.
One less thing that can go wrong.
I didn't use current limiting either.
I've seen a few F5 builds where the power mosfets are mounted to the heatsinks, and the boards to the bottom panel. The thermistor is no where near the mosfets.
That's not a good idea I guess.
Perhaps they were relying on the air temperature inside the case to operate the thermistors ?
I am trying to go through all the thread and make some steps in the construction at the same time. I read the article and I am at page 128 of the thread. I am sure that the answers to my questions are in the remaining 794 pages...
Anyway...few questions:
1) I understand that the MOSFET do not need any matching, just avoid IR brand. I have Vishay, it should be OK.
2) For the Jfet, I read that they should be between 6 and 8 mA and some matching is beneficial. How well matched they should be ? What's the max difference I can tolerate ?
3) do the jfet of two different channels have to be matched ?
4)About components, where the use of NH resistors is beneficial ? I plan to use dale RN55. Is the use of carbon oxide recommended for gate stoppers ?
Thanks,
Davide
Anyway...few questions:
1) I understand that the MOSFET do not need any matching, just avoid IR brand. I have Vishay, it should be OK.
2) For the Jfet, I read that they should be between 6 and 8 mA and some matching is beneficial. How well matched they should be ? What's the max difference I can tolerate ?
3) do the jfet of two different channels have to be matched ?
4)About components, where the use of NH resistors is beneficial ? I plan to use dale RN55. Is the use of carbon oxide recommended for gate stoppers ?
Thanks,
Davide
1 . difference is - slightly darker sound ( Papa sez "tube bloom" ) with IRF P type
2 . say that range of 10% is OK
3. not necessary , if you aren't of "match them all" type ; this isn't RIAA EQ 😉
4. pick your poison ; some use carbons for gate stoppers
2 . say that range of 10% is OK
3. not necessary , if you aren't of "match them all" type ; this isn't RIAA EQ 😉
4. pick your poison ; some use carbons for gate stoppers
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