Hello @Markw4
it´s possible that the flip flop could generate runt pulse by violating setup time when Oscillator switched?
JP
it´s possible that the flip flop could generate runt pulse by violating setup time when Oscillator switched?
JP
Hi JPS64,
You should have an oscilloscope to check for time sequencing between the clock and the I2S signals to make sure they meet setup time. If a problem, you you can delay I2S signals by various means until they do meet setup.
You should have an oscilloscope to check for time sequencing between the clock and the I2S signals to make sure they meet setup time. If a problem, you you can delay I2S signals by various means until they do meet setup.
Is the ESS chip actually that sensitive to having I2S signals present before MCLK? what if the ESS is held in reset until after MCLK is stable?
The problem would be a D-flip flop if one is used for reclocking.
Regarding SD dacs, the datasheet may state that phase of MCLK does not matter so long as it is synchronous with I2S signals (IIRC ESS and AKM say that). IME that may not always be perfectly true but the dac should still work to spec regardless of phasing. For me at least, sometimes a particular phasing sounds slightly better. That's something I wrote about long ago when experimenting with ES9038Q2M in DSD mode. On the other hand, for I2S signals DATA may need to meet a setup time spec relative to BCLK and LRCK. Usually there are timing diagrams in datasheets to show that. One possible purpose of reclocking might be to get that timing dialed in really well. Depends on the particular situation of course.
Regarding SD dacs, the datasheet may state that phase of MCLK does not matter so long as it is synchronous with I2S signals (IIRC ESS and AKM say that). IME that may not always be perfectly true but the dac should still work to spec regardless of phasing. For me at least, sometimes a particular phasing sounds slightly better. That's something I wrote about long ago when experimenting with ES9038Q2M in DSD mode. On the other hand, for I2S signals DATA may need to meet a setup time spec relative to BCLK and LRCK. Usually there are timing diagrams in datasheets to show that. One possible purpose of reclocking might be to get that timing dialed in really well. Depends on the particular situation of course.
Last edited:
The ES90382M datasheet for example doesn't say anything at all about data lines:
I would assume that I2S signals can be present right after DVCC is supplied. As I didn't try that myself (And cannot atm, I'm currently routing my DAC PCBs) that was a question for the more experienced ones - @Markw4 maybe?
I would assume that I2S signals can be present right after DVCC is supplied. As I didn't try that myself (And cannot atm, I'm currently routing my DAC PCBs) that was a question for the more experienced ones - @Markw4 maybe?
Attachments
Ah, I see you're talking about setup and hold times of data on the I2S DATA lines regarding the rising edge of MCLK... So @JPS64 was talking about a runt pulse from the MCLK when switching oscillators... Wouldn't it be good practice to hold the ESS in reset when switching MCLK to another oscillator?
I2S runt pulses could be produced by the the D-flip flop used for reclocking if its setup time spec is not met. Thought that is what @JPS64 was asking about?
Regarding startup sequencing of the dac, the data sheet page attached to #7425 would seems to me to apply in principle when switching clocks as far as asserting a reset. Don't know if it matters much in practice. Muting the analog audio outputs when there could be pops or other noises produced during dac mode changes might be a good idea.
Regarding startup sequencing of the dac, the data sheet page attached to #7425 would seems to me to apply in principle when switching clocks as far as asserting a reset. Don't know if it matters much in practice. Muting the analog audio outputs when there could be pops or other noises produced during dac mode changes might be a good idea.
MAX6126 is a good substitute, but honestly, you can use any reasonable reference, just filter it well, with a passive filter before you send the voltage to the opamp.
+1
Proper RC filtering and decoupling directly at the opamp's input is probably far more important than the noise voltage of the reference itself.
Proper RC filtering and decoupling directly at the opamp's input is probably far more important than the noise voltage of the reference itself.
Some people have used LT3042 or LT3045. Off-the-shelf boards may use class-2 ceramic caps, which I would not recommend for this type of use. 805 SMD film caps have been tried by some people for LT304x regulators. The film caps are much more linear and time-invariant as verses class-2 ceramic.
I would strongly recommend using those "non linear, time variant" capacitors for filtering and decoupling purposes.
The op amp buffered reference voltage is a band aid solution that uselessly takes board real estate, without any significant advantage; if LT304X is deemed not good enough (although IMO it would work perfectly fine), use something like the ADM7154 for AVCC. I am currently using the ADM chips, decoupled with 10uF X7R 0603 of those "horrible" capacitors, and got SINAD under -120dB, at the DAC output.
Film capacitors for decoupling is yet another dumb idea of the Golden Ear priests and their posse, they are actually not even recommended to use (for stability reasons) by most of the regulators/references chips manufacturers.
The op amp buffered reference voltage is a band aid solution that uselessly takes board real estate, without any significant advantage; if LT304X is deemed not good enough (although IMO it would work perfectly fine), use something like the ADM7154 for AVCC. I am currently using the ADM chips, decoupled with 10uF X7R 0603 of those "horrible" capacitors, and got SINAD under -120dB, at the DAC output.
Film capacitors for decoupling is yet another dumb idea of the Golden Ear priests and their posse, they are actually not even recommended to use (for stability reasons) by most of the regulators/references chips manufacturers.
People have tried ADM715x for AVCC. That's what Twisted Pear uses for their Buffalo dacs. I bought some of their regulators to try. Didn't like the sound myself. They did sound a little better to me with an extra load resistor to ground though. Opamp buffers sound better to me.
Also tried the same ADM715x regulator for VCCA, and for DVCC. They worked fine for that, no complaints.
Also tried the same ADM715x regulator for VCCA, and for DVCC. They worked fine for that, no complaints.
Evaluating performance by ear, your specialty.
Useless to ask what makes you believe others will arrive at the same conclusions? Except you are a self appointed Golden Ear.
Useless to ask what makes you believe others will arrive at the same conclusions? Except you are a self appointed Golden Ear.
And meantime, you could refrain from spreading the same expired malarkey.
Read again what you are posting. You are not sharing your experience, you are sharing what you believe are authoritative advice, and "some people" (unidentified) results (using unknown methods). Your patented FUD recipe.
Read again what you are posting. You are not sharing your experience, you are sharing what you believe are authoritative advice, and "some people" (unidentified) results (using unknown methods). Your patented FUD recipe.
Recently you guys arguing in another thread were threatened with at least two weeks of read only. You wait a couple of days then come over here and start doing the same thing again.
Hopefully the powers that be will take note.