RFScheer said:
Why is this so hard? The DAC-AH is the yellow, stair-stepped trace. In my post I said: “…an unfiltered DAC will have stair steps…” and “…the normally unfiltered DAC-AH…” and “…the AN DAC 1.2, which is NOS with a second order LP filter…” I honestly thought those clues would be sufficient to identify which trace was which.
No typo.
I guess you weren’t paying attention when I wrote: “…the ’scope is looking at the analog output of the DACs. This is the same signal that gets fed to the audio amplifier.” If you guys aren’t going to read what I write, why should I bother?
It’s the DAC-AH and the flat top is caused by DAC linearity errors at the extremes of its range. That’s what I was trying to explain and used the pictures as illustration. I give up.
poynton said:
Yes, the data comes off the CD in a serial format. Yes, a parallel DAC chip requires additional chips, such as shift-registers, latches, clocks, etc. Yes, a serial, multi-bit DAC chip includes exactly the same logic, BUT: In the case of the parallel DAC, all those bits and pieces are separate and can be easily isolated from each other, electrically and physically. That’s very good for performance but it’s very bad for the bean counters. More parts = more cost. Serial DACs are good because they reduce costs and complexity but it means the clocked, digital circuits are stuffed into the same chip package as the D/A converter, which doesn’t perform as well in such a noisy environment.
I think you’ve got it backwards. I am using techno stuff to understand why the DAC-AH sounds so bad.
Getting back to the subject.............
ULAS,
You have had your moan about 'clock-mongers', You've had a moan about the DAC-AH [ and indirectly about the TDA1543, which you obviously do not like ] and you have had a moan about contributors to the thread.
So, please, NO MORE !!!!
Getting back to the original question:-
Is settling time of DACs and other components important and overlooked ???
The evidence from the plots provided by Ulas and the data sheets {eg TDA1541 } would seem to suggest that settling times in the microsecond region should be of more concern than the picosecond clock 'jitter' times.
I would like to throw this opinion into the pot......
Neither is important in absolute terms.
Both are translated into timing errors so that the wavefront at the ear arrives a short time early or late. The effect that this would have is to shift the perceived image forward or back on the soundstage. An error of 1 usec [ assuming the image was directly in front ] would 'move' the image by 1 millionth of 1100 feet !!
That assumes that the error is 'common mode' that is both channels are affected equally and in the same direction.
Timing errors that affect the channels differently would be perceived as an image which moves left or right or as it is more commonly called ' a blurring of the image'.
So the challenge as I see it is to design and build a DAC in which the timing errors [ settling and jitter ] are at the same time both minimised and of equal magnitude and direction in both channels.
Whether that can be achieved and how [ or indeed has it already been achieved ] I leave open to discussion [ not mudslinging ]
Andy
ULAS,
You have had your moan about 'clock-mongers', You've had a moan about the DAC-AH [ and indirectly about the TDA1543, which you obviously do not like ] and you have had a moan about contributors to the thread.
So, please, NO MORE !!!!
Getting back to the original question:-
Is settling time of DACs and other components important and overlooked ???
The evidence from the plots provided by Ulas and the data sheets {eg TDA1541 } would seem to suggest that settling times in the microsecond region should be of more concern than the picosecond clock 'jitter' times.
I would like to throw this opinion into the pot......
Neither is important in absolute terms.
Both are translated into timing errors so that the wavefront at the ear arrives a short time early or late. The effect that this would have is to shift the perceived image forward or back on the soundstage. An error of 1 usec [ assuming the image was directly in front ] would 'move' the image by 1 millionth of 1100 feet !!
That assumes that the error is 'common mode' that is both channels are affected equally and in the same direction.
Timing errors that affect the channels differently would be perceived as an image which moves left or right or as it is more commonly called ' a blurring of the image'.
So the challenge as I see it is to design and build a DAC in which the timing errors [ settling and jitter ] are at the same time both minimised and of equal magnitude and direction in both channels.
Whether that can be achieved and how [ or indeed has it already been achieved ] I leave open to discussion [ not mudslinging ]
Andy
Hi Ulas,
You have certainly managed to grab the attention here and at DiyHiFi.
You must be happy...????
I am not going to comment your ways on achieving press coverage.
However, your comments about jitter, settling time, the whole concept of digital audio and 8 X 1704 DAC design sound very interesting and promising. Could you tell us more about your design?
Extreme_Boky
You have certainly managed to grab the attention here and at DiyHiFi.
You must be happy...????
I am not going to comment your ways on achieving press coverage.
However, your comments about jitter, settling time, the whole concept of digital audio and 8 X 1704 DAC design sound very interesting and promising. Could you tell us more about your design?
Extreme_Boky
Ulas, just so I get this straight, are you saying that jitter and all the ways of dealing with it, are completely insignificant in any DAC with op amps in the signal path? In other words, unless the design includes only passive I/V and no op amps whatsoever, all the re-clocking and ASRC's are completely bogus and worthless?
Despite from all the unpleasant aspects of this thread, there's something to think about in it.
I somewhat can't believe that settling time induced amplitude errors are such a big problem as Ulas tries to tell us. Simply because in reality, a DAC's distortion level is much lower as it should be if there are such big problems. Some simple calculations:
Given a non-OS system with TDA1543. That one's specified with a +/- 1 LSB settling time of 0.5 microseconds. A CD sample is 1/44100 Hz = 22.7 microseconds long. So the problem (at least within +/- 1 LSB boundaries, what should be more than sufficient) only occurs during the first 2.2 percent of the sample!
Not that big problem, but nervertheless one to be aware of.
Let's consider PCM 1704 at full speed (96 kHz):
TI specifies 0.2 µs settling time for +/- 0,0003 % of a full scale output current swing; I haven't calculated it, but this should be as well somewhat in the +/- 1 LSB region.
A 96 kHz sample takes 10.4 µsec, so here, the settling time takes 1.9 Percent of the whole sample.
The conclusion is simple: no need to trash those non-OS DACs, the problem is always the same: making the chips faster decreases the problem, higher sample rates increase it.
May someone convince me that I am talking complete nonsense... 😀.
I somewhat can't believe that settling time induced amplitude errors are such a big problem as Ulas tries to tell us. Simply because in reality, a DAC's distortion level is much lower as it should be if there are such big problems. Some simple calculations:
Given a non-OS system with TDA1543. That one's specified with a +/- 1 LSB settling time of 0.5 microseconds. A CD sample is 1/44100 Hz = 22.7 microseconds long. So the problem (at least within +/- 1 LSB boundaries, what should be more than sufficient) only occurs during the first 2.2 percent of the sample!
Not that big problem, but nervertheless one to be aware of.
Let's consider PCM 1704 at full speed (96 kHz):
TI specifies 0.2 µs settling time for +/- 0,0003 % of a full scale output current swing; I haven't calculated it, but this should be as well somewhat in the +/- 1 LSB region.
A 96 kHz sample takes 10.4 µsec, so here, the settling time takes 1.9 Percent of the whole sample.
The conclusion is simple: no need to trash those non-OS DACs, the problem is always the same: making the chips faster decreases the problem, higher sample rates increase it.
May someone convince me that I am talking complete nonsense... 😀.
Don't just moan about poor performance of TDA1543 and global conspiracy to force it upon unsuspecting consumers. If you want fast settling time and parallel interface, use AD9726 or AD9779.
I don't think the type of interface is of any means here.
Even on a serial input DAC, a complete data word is clocked into the converting structure before conversion starts.
Parallel interface helps reducing the speed on the digital input side, nothing more.
On the other hand, using high speed non-audio DACs may be an interesting idea.
Even on a serial input DAC, a complete data word is clocked into the converting structure before conversion starts.
Parallel interface helps reducing the speed on the digital input side, nothing more.
On the other hand, using high speed non-audio DACs may be an interesting idea.
HBarske said:
You are viewing the issue in absolute terms when you should be viewing it in relative terms. i.e the relative insignificance of 1ps of clock jitter compared to the much much larger settling time.
Not sure if I understand you.
The settling time itself is not the problem, but the amplitude errors during settling time.
Jitter - as far as I know - is something completely different, a shift in time. I don't want to judge those two phenomens one against the other, as to me they seem something completely different.
The settling time itself is not the problem, but the amplitude errors during settling time.
Jitter - as far as I know - is something completely different, a shift in time. I don't want to judge those two phenomens one against the other, as to me they seem something completely different.
HBarske said:
One cannot separate one from the other. Though jitter ultimately shows up as an amplitude error, unless it is a significant amount, it is dwarfed by any error due to settling time.
You tell me. Settling time starts from a clock edge and takes Xus. If there is any jitter on the triggering clock edge the settling time will either start late or early, so settling time is now (X + Y)uS or (X - Y)uS, Y being the timing error due to jitter . How late or early must the edge be, i.e how much jitter, for the amplitude error due the edge being out of position in time to mask the amplitude error due to a finite settling time?
May be this description can help you all: www pages "What is wrong with digital audio" and the page about exponential settling and slew-rate limited settling.
Also the relation between settling time and jitter is discussed. I made these pages recently and I was not aware of the discussions on DIY audio.
--------------------
Frans Sessink
Also the relation between settling time and jitter is discussed. I made these pages recently and I was not aware of the discussions on DIY audio.
--------------------
Frans Sessink
May be I can contribute to this discussion.
This information can help you probably: settling behavior and distortion is discussed on my homepage (www.brightnoise.nl). See the pages "What is wrong with digital audio" and "DAC settling and perceived audio performance".
DAC settling time (in nanoseconds) exceeds jitter (in picoseconds) by far. Settling time is causing a signal-dependent, or voltage-jump-dependent, delay and causes distortion, as explained on www. There is also a solution given for clock jitter. This solution works even after a poor S/P-DIF receiver. That is explained in a short document.
My interest is more the technical side; my ears are probably not good enough to hear the differences in audio quality that you are talking about.
Frans Sessink
frans.sessink.nl
(active on DIY audio since today, 2010 May 21, 09:00 CET)
This information can help you probably: settling behavior and distortion is discussed on my homepage (www.brightnoise.nl). See the pages "What is wrong with digital audio" and "DAC settling and perceived audio performance".
DAC settling time (in nanoseconds) exceeds jitter (in picoseconds) by far. Settling time is causing a signal-dependent, or voltage-jump-dependent, delay and causes distortion, as explained on www. There is also a solution given for clock jitter. This solution works even after a poor S/P-DIF receiver. That is explained in a short document.
My interest is more the technical side; my ears are probably not good enough to hear the differences in audio quality that you are talking about.
Frans Sessink
frans.sessink.nl
(active on DIY audio since today, 2010 May 21, 09:00 CET)
I just had a look at your website. Interesting that you asked the question 'Do you trust the speed of the op-amps in the application diagram from the PCM1794?', its something that I've been pondering on and off for a while. If you look at the schematic more closely, you'll see that TI has a relatively large feedback capacitor around the opamp there. This prevents the 5534 going anywhere near slew rate limiting. However, to my ears it tends to wipe out the ambience of a recording. Haven't figured out why, but since changing to a considerably lower value of cap in that position on my Asus ST soundcard, I haven't looked back.
Frans, I just read through your excellent document. You understood and explained what the thread starter and other contributors have not: distortion may be caused by limited slew rate, not by (linear, RC time constant-determined) settling time. One thing is not clear: is there any slew-rate induced distortion present in common high-quality DACs? In other words, do you have any measurement evidence for such distortion? You mentioned that manufacturers of DAC chips do not specify slew rate (opamp manufacturers do so). Thanks, Laszlo
DAC settling
Laszlo,
the settling speed of a flash DAC depends on the actual binary value at the input. The number of current sources that is active to generate the (corresponding to the binary word) output current varies from word to word. The output capacitance is in this way modulated and so is the settling time.
The settling time of a TDA1543 is specified as "within 500 ns". The measured settling time shows variations in the tens of nanoseconds, depending on the actual value at the output. So the DAC modulates the signal delay from sample to sample. My conclusion is that the influence of this stochastic group delay modulation is higher than the jitter from a good clock, like the Tent-lab clocks.
This "modulated capacitance" is probably an explanation for the sound differences as a function of the load impedance of a DAC with current-output.
The varying capacitance problem can be solved with a proper I-to-V converter. Most op-amps can not handle the fast settling of the DAC current and will introduce a slew-rate limitation. Also the DAC itself has internally a slew-rate limitation. (My DAC is a single TDA1543).
*****
There is however a simple solution for the DAC settling problem errors. The solution combines the settling-induced errors and the exact timing of the output samples (the jitter problem). The circuit is very simple and understanding that solution does not require a university degree or special education.
Explanation in simple words: the DAC output signal is sampled AFTER full settling. In this way the accuracy of the signal level is almost as good as a static (DC) DAC conversion. The sample-hold is clocked by a synchronized recovered clock that solely determines the timing of the output signal (or jitter). The sample-hold settling is free from slew-rate limitation and settles as an RC-delay (constant group delay; no signal-dependent variations). And also part of the system is an I-to-V converter with an op-amp. The slew-rate limitation of this I-to-V converter is not affecting the audio quality in this design, since the sample-hold is taking a sample later-on in time, after final settling of this suspicious signal processing element.
What can be done more in a NOS-DAC than this: output the correct sample value at the correct moment and remove the stochastic variable group delay?
The system is described on frans.sessink.nl or www.brightnoise.nl and is already available on the internet for months.
The name for the combination of the two ingredients:
Synchronized Exponential Settling NOS DAC
Stereo is back again without the scratches, the limited channel separation, the limited frequency response and the rumble, the hum and the noise from vinyl.
Enjoy!
Frans Sessink
Laszlo,
the settling speed of a flash DAC depends on the actual binary value at the input. The number of current sources that is active to generate the (corresponding to the binary word) output current varies from word to word. The output capacitance is in this way modulated and so is the settling time.
The settling time of a TDA1543 is specified as "within 500 ns". The measured settling time shows variations in the tens of nanoseconds, depending on the actual value at the output. So the DAC modulates the signal delay from sample to sample. My conclusion is that the influence of this stochastic group delay modulation is higher than the jitter from a good clock, like the Tent-lab clocks.
This "modulated capacitance" is probably an explanation for the sound differences as a function of the load impedance of a DAC with current-output.
The varying capacitance problem can be solved with a proper I-to-V converter. Most op-amps can not handle the fast settling of the DAC current and will introduce a slew-rate limitation. Also the DAC itself has internally a slew-rate limitation. (My DAC is a single TDA1543).
*****
There is however a simple solution for the DAC settling problem errors. The solution combines the settling-induced errors and the exact timing of the output samples (the jitter problem). The circuit is very simple and understanding that solution does not require a university degree or special education.
Explanation in simple words: the DAC output signal is sampled AFTER full settling. In this way the accuracy of the signal level is almost as good as a static (DC) DAC conversion. The sample-hold is clocked by a synchronized recovered clock that solely determines the timing of the output signal (or jitter). The sample-hold settling is free from slew-rate limitation and settles as an RC-delay (constant group delay; no signal-dependent variations). And also part of the system is an I-to-V converter with an op-amp. The slew-rate limitation of this I-to-V converter is not affecting the audio quality in this design, since the sample-hold is taking a sample later-on in time, after final settling of this suspicious signal processing element.
What can be done more in a NOS-DAC than this: output the correct sample value at the correct moment and remove the stochastic variable group delay?
The system is described on frans.sessink.nl or www.brightnoise.nl and is already available on the internet for months.
The name for the combination of the two ingredients:
Synchronized Exponential Settling NOS DAC
Stereo is back again without the scratches, the limited channel separation, the limited frequency response and the rumble, the hum and the noise from vinyl.
Enjoy!
Frans Sessink
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