That is what i thought, which is why there is a need for a firmware 'update' but he said all he need is to know how to connect . The Amanero (and its clones) should be using 512fs MCK.
@MrHifiTunes HC is not valid, it must be HCT
https://www.tme.eu/be/en/details/cd74hct164m/shift-registers/texas-instruments/
you can buy there other parts as well 😉
https://www.tme.eu/be/en/details/cd74hct164m/shift-registers/texas-instruments/
you can buy there other parts as well 😉
PCM63P and LT1354. Finally have it on a board and able to take to the big system.
What do you think about this USB-I2S board to use with Miro's CPLD. It has good Accusilicon clocks and possibility to upgrade to Crystek 975 or AS318-B
https://www.aliexpress.com/item/4001033056460.html?spm=a2g0s.9042311.0.0.5efd4c4d1Sn46p
https://www.aliexpress.com/item/4001033056460.html?spm=a2g0s.9042311.0.0.5efd4c4d1Sn46p
They are only using NDK crystals now. The board is unable to take the Crytek CCHD 975. I think it can allow CCHD 575 , but then the decoupling capacitor ( I am assuming) would have to be removed. Not really a good idea perhaps?
Well tjese usb clones are less good most of the time with no guaranty the chips are welll programmed . Why not get one from York for the sale price here???
However to be fair, Xing is not a Amanero clone. Just like York, it is the maker's own solution in the foot print of the Amanero.
However, it lacks the flexibility of the York.
However, it lacks the flexibility of the York.
for I, it willl be the same at the end as there is layer more after: a FGPA (miro's) to handle the PCM for the two DAC chips.
Whatever the xtals, each fgpa after add jitter, ground-bounce, decoupling behavior of active devices... and should ask near recloking. The less the better or the last FGPA must be clocked /slaved by the reference clock which is anyway before as embeded on the "clone like".
With shorter solution like Yoke or JLSounds, reclocking at the feet of the dac chips is surely not mandatory or difference certainly hard to hear. The few added jitter comes from the last active fgpa/cpld I assume (?). Ons stage logicallly seems better to me.
I have something like Tesla in my main DAC with IanCANDA I2S to PCM on a third board : but it is slaved by the MCLK and in another clock domain than the first USB to I2S first stage (here a Wave i/o). And all is impedance controlled with uf-l cables from the beginning to the dac chips. Dping combo with two boards that have diffference uf-l arrengment is never good (bad sheiling, impedance problems, more bouncing; not isolated return path and crosstalk most of the time).
But at the end, if you ask me, I really believe only on the final listening test beyond theory !
Whatever the xtals, each fgpa after add jitter, ground-bounce, decoupling behavior of active devices... and should ask near recloking. The less the better or the last FGPA must be clocked /slaved by the reference clock which is anyway before as embeded on the "clone like".
With shorter solution like Yoke or JLSounds, reclocking at the feet of the dac chips is surely not mandatory or difference certainly hard to hear. The few added jitter comes from the last active fgpa/cpld I assume (?). Ons stage logicallly seems better to me.
I have something like Tesla in my main DAC with IanCANDA I2S to PCM on a third board : but it is slaved by the MCLK and in another clock domain than the first USB to I2S first stage (here a Wave i/o). And all is impedance controlled with uf-l cables from the beginning to the dac chips. Dping combo with two boards that have diffference uf-l arrengment is never good (bad sheiling, impedance problems, more bouncing; not isolated return path and crosstalk most of the time).
But at the end, if you ask me, I really believe only on the final listening test beyond theory !
@diyiggy I never used FPGA for DACs, in my case it is CPLD. CPLD has less jitter than FPGA. CPLD can have like 50ps and highly depends on how the code is written (how complicated is design) ... my code is very simple and proven how it sounds 😉 ... FPGA is different from CPLD, very different (much more complicated and easily can have more jitter).
2 to 10 pico second?
Anyway, the problem is not your design is bad , that is not was I said btw but that you have to add a stage more in Tesla scenario.
I'm not sure it is better in that scenario than the 74hcxxx on the same board than the dac chips. Layout matters.
I dunno if someone has the machines to measure that.
Ah, I should be able before the end of the week to test my v5 4 layers board with Grunf's BOM but the feedback cap which is a simple TDK C0G soft terminations).
Anyway, the problem is not your design is bad , that is not was I said btw but that you have to add a stage more in Tesla scenario.
I'm not sure it is better in that scenario than the 74hcxxx on the same board than the dac chips. Layout matters.
I dunno if someone has the machines to measure that.
Ah, I should be able before the end of the week to test my v5 4 layers board with Grunf's BOM but the feedback cap which is a simple TDK C0G soft terminations).
Attachments
Which CPLD are you using today?
I used MAX7000x and MAX3000A in the past, but now they are obsolete.
If there anything with 3.3v or 5v VCC available now with a price less than a wing from F22?
(Better with in-system programming via ByteBlaster)
Alex.
@diyiggy Both are good, either HCT registers (with untouched LRCK) or CPLD
@altor EPM240T100C5N is still available everywhere in a fair price (new or aliexpress) and performs great - this is my choice nr1 😉 ... even the cheapest 5M80ZM64 with 64 macrocells can be enough for this DAC conversion and is very tiny (yes, the supply voltage is only 1.8 for this and you need voltage convertors) 😉
@altor EPM240T100C5N is still available everywhere in a fair price (new or aliexpress) and performs great - this is my choice nr1 😉 ... even the cheapest 5M80ZM64 with 64 macrocells can be enough for this DAC conversion and is very tiny (yes, the supply voltage is only 1.8 for this and you need voltage convertors) 😉