@Hidy Thank you for all your hints
The stop-clock PCB contains gaps in the GND plane, between digital and analog, and GNDs are connected under DAC chips ... it can improve something, or maybe not, hard to say without testing
I still think these LDO regulators have big problem with capacitors. Can you test the 78/79xx regulators how they perform in comparison with the LDOs?
@jpk73 See the main board diagram on the first page (CDS3main_R4.pdf)
There is only one CLK common for both DACs, therefore it cannot be stopped.
I still think these LDO regulators have big problem with capacitors.
It means, DL and DR are aligned internally in the PMD200 chip for one clock.
@jpk73 Aligning I2S DATA with stopped clock logic that way needs a lot of glue logic (or CPLD, which only a few can program at home ). If I come up with something simple, I'll make a diagram
Stop-Clock2 - both channels are aligned together and with one stopped BCK moved for Left and Right DAC.