Ok, the 2mA per channel "disappear" in your NE5534 I/U conversion circuit and return to your star ground via this.
Could you try removing the 5534 and use resistors for I/U conversion to AGND. This will be more clear for the TDA1541 currents.
I'm especially interested in the Zero and Full scale cases.
Because now we still do not know if AOL/AOR flow indirectly into AGND or DGND (I think DGND, but I need to think more).
Thor
Will do tomorrow.
DGND and AGND are not involved in the bit currents. DGND has a role only in the digital signal processing. AGND is only a reference, as you correctly wrote earlier. The return path of the analog output current is the -15 V pin. The sum of +5 V current (analog section only!) and the L, R current flowing in the analog outputs equals the -15 V pin current flowing out, and it is constant. If the analog output currents increase, the +5 V current decreases.
The external source of the analog output currents can be anything as long as it has a common reference to -15 V or AGND, whichever is more convenient. I think AGND is better because the output voltage compliance +/- 25 mV is referred to it.
DGND and AGND are not involved in the bit currents. DGND has a role only in the digital signal processing. AGND is only a reference, as you correctly wrote earlier. The return path of the analog output current is the -15 V pin. The sum of +5 V current (analog section only!) and the L, R current flowing in the analog outputs equals the -15 V pin current flowing out, and it is constant. If the analog output currents increase, the +5 V current decreases.
The external source of the analog output currents can be anything as long as it has a common reference to -15 V or AGND, whichever is more convenient. I think AGND is better because the output voltage compliance +/- 25 mV is referred to it.
If I remember correctly, John @ecdesigns (or someone else?) proposed an I/V converter built around an NPN transistor. The TDA chip output was fed to the emitter, the base was grounded (with some level shift to keep the emitter at zero volt), and the collector resistor was connected to +5 V. The output voltage was taken from the collector. This way the +5 V supply delivered constant current to the TDA + I/V.
I think it is?
(Because the data aree loaded and stored in registers. Waiting for the LE impuls. Rising edge.)
.
'
Ok, I created a Tequivalent of the test circuit in TINA:
Everything on the left is the TDA1541.
The 7.19k resistors to +15V represent the active I/U conversion with I/U conversion resistors and Op-Amp Positive output path.
The four leftmost current sources are the audio part and each pair changes complementary.
Thor
That is not "conversion". It has no direct link to the analog part, other than switching bits.
The whole concept of "conversion" comes from SAR ADC's, which is in effect a R2R or similar multibit DAC with a comparator to input signal and logic that uses "successive approximation", until it has a result. This is normally best done with as many noise sources as possible off, including stopped bit and woird clock, until the ADC has a result and releases the interrupt line.
It is meaningless for a DAC.
It makes no real difference to the LE edge if BCK is switching or not.
Yes, that is the datasheet. But perhaps in SIM Mode the actual output still happens at the first BCK Edge after LE?
We need the analogue output on the screen as well, compared to LE.
Thor
I think John mainly used Mosfets.
But yes, that is the principle.
Of course, if we go balanced, we also have constant currents (+/- 1/2 LSB).
Thor
Lets use the term "sample at output" as int the documents. Considering that LE event determines when the previously stored datas will send to analog output.
Than "conversion" will be more of this events, of sample at output, continuously...
LE = F(SR)
Maybe, because in the datasheet, if I am remember well, stated that the time after LSB stored and rising edge of the LE can be 0s. So sample at output event can be instant after last bit of serial data stored. I think in TDA1541A PDFs stated.
It would be nice info to have it with time sync to see what the delay between LE and apearing of analog event?
I agree 100%.
The items are sold after the Alexandre posted informations. So it is huge probability that buyer was reading the this topic?
cheers.
Must be someone in the UK. I enquired and was told the item sell on e-bay UK only and must be shipped to an UK address and paid via UK e-bay.
My e-bay was registered to Hong Kong and I needed shipment to Thailand, so no go. The seller did mention a lot of interest.
I suspect that several people have watch set up on e-bay and other platforms for TDA1541 related stuff. I do.
Thor
Ok, lets look closer at the TDA1541 current flows and adjust some of our guesses:
We have current flow from -15V of 26.45mA into +5V, AOL, AOR and AGND. Around 16mA + 4mA flow into +5V.
We have 39mA flowing from -5V into DGND, making up the largest DC current loop.
We also have ~10mA of current flowing from DGND into +5V, so ~10mA of the current flow in DGND from -5V are cancelled out.
My personal concusions are as follows.
All logic is ECL between DGND and -5V, essentially Textbook ECL.
The +5V supply supports only the DEM circuit and the digital inputs.
The digital inputs then look roughly like this:
The above circuit draws almost 5mA from the Vcc (+5V rail), if running a little less current for a slower design, 2.5mA each for 4 inputs equalling 10mA makes sense.
Vcc (+5V) thusly is subject to current variations caused by clocks and data via the emitter resistor loads of the input transistors subject to signal dependent variation and to current variations directly signal related.
Thankfully current variation through the emitter resistor is limited, as the emitter can only swing up to ~2.4V before being clamped by diodes (to substrate - more noise sources) and down to around 0.6V, limiting swing. So we see again, ideally we both attenuate (avoid the clamping diodes to conduct) and slew rate limit (avoid conducting edges into the substrate.
So DGND -> +5V is a loop that needs low impedance from essentially DC to high harmonics of the clock, so it not modulated by either audio or clocks, as any of this modulation can increase jitter.
Vee5 (-5V) we can see is subject only balanced circuit with some H2/3 of the clocks or data flowing from -5V to DGND, but we also have currents circuilating with Vcc (+5V) that are clock and data dependent.
So Vee5 (-5V) -> DGND needs low impedance at high frequencies but is essentially agnostic of signals even at actual clock frequencies. But Vee5 (-5V) to Vcc (+5V) needs close decoupling to circularise the data and clock related currents
Having DGND at the opposite side and end of the IC is really, really inconvenient for this decoupling to DGND.
Vcc to Vee5 on the other hand is fairly trivial.
For Vcc (+5V) and Vee15 (-15V) the previous analysis mainly holds, except AGND is not a key power supply node, but the Vcc (+5V) -> Vee15 (-15V) loop is most important
AGND doesn't seem to much, just provide some bias for circuitry referenced to Vee15 (-15V).
So we have to adjust the "optimum" decoupling and power supplies a little.
AGND and DGND can be separated by quite a substantial impedance, but the main current flow is always DGND.
My thoughts...
One 20V supply for Vcc -> Vee15 will handle audio AND inputs. A low impedance shunt "DC to light" is needed here, because it is a VERY MIXED UP mixed signal pin Vcc to DGND. Vee15 to DGND is also fairly critical due to the VHF glitches created by the DEM circuit.
A 10V shunt regulator from a 30V Supply (+/-15V) is entirely workable and circularises any signal current injected into +15V by the I/U conversion using Op-Amps.
In this case it is disrecommended to apply offset current cancellation, instead accept that the I/U conversion OPA has a significant positive DC on the output. This voltage and the DC current flowing in the I/U conversion resistor bias the OPA into Class A for the whole signal range. In fact, an extra pulldown to Vee5 or Vee15 may be used for emitter follower outputs to improve their open loop output impedance to absorb "glitches" passing into the output via the parallel capacitor on the I/U conversion resistor. The situation is less clearcut for RTO OPA's, which have collector outputs.
To make all shunts work correctly, we need to draw an extra bias of ~10mA from Vee15 to DGND.
So our +15V -> Vcc (+5V) shunt is 10V & passes an average 35mA (0.35W dissipation - TO-92 TL431 will do) and our VCC Shunt handles ~5mA / 5V.
DEM decoupling remains at Vee15, no change here.
A separate 5V supply between DGND and Vee5 supplies the digital part. This is FAIRLY uncritical, but still, watch common mode noise leakage.
So 20V or 30V DC @ ~ 50mA (depending on analogue circuit) for "analogue" and 5V @ 50mA for digital cover the TDA1541 stand alone plus analogue stages cover that part.
Really, a DIP32 case with AOLN/AORN and VCC-IN pin's added and DGND-IN (substrate!) at a pin next to inputs, DGND logic at a pin next to Vcc & Vee5 and AGND + Vee15 next to each other would have made life with the TDA1541 ever so much easier.
But unless we can send someone back in time to tell the guy's at Philips, I suspect we have to live with the IC as is.
Thor
We have current flow from -15V of 26.45mA into +5V, AOL, AOR and AGND. Around 16mA + 4mA flow into +5V.
We have 39mA flowing from -5V into DGND, making up the largest DC current loop.
We also have ~10mA of current flowing from DGND into +5V, so ~10mA of the current flow in DGND from -5V are cancelled out.
My personal concusions are as follows.
All logic is ECL between DGND and -5V, essentially Textbook ECL.
The +5V supply supports only the DEM circuit and the digital inputs.
The digital inputs then look roughly like this:
The above circuit draws almost 5mA from the Vcc (+5V rail), if running a little less current for a slower design, 2.5mA each for 4 inputs equalling 10mA makes sense.
Vcc (+5V) thusly is subject to current variations caused by clocks and data via the emitter resistor loads of the input transistors subject to signal dependent variation and to current variations directly signal related.
Thankfully current variation through the emitter resistor is limited, as the emitter can only swing up to ~2.4V before being clamped by diodes (to substrate - more noise sources) and down to around 0.6V, limiting swing. So we see again, ideally we both attenuate (avoid the clamping diodes to conduct) and slew rate limit (avoid conducting edges into the substrate.
So DGND -> +5V is a loop that needs low impedance from essentially DC to high harmonics of the clock, so it not modulated by either audio or clocks, as any of this modulation can increase jitter.
Vee5 (-5V) we can see is subject only balanced circuit with some H2/3 of the clocks or data flowing from -5V to DGND, but we also have currents circuilating with Vcc (+5V) that are clock and data dependent.
So Vee5 (-5V) -> DGND needs low impedance at high frequencies but is essentially agnostic of signals even at actual clock frequencies. But Vee5 (-5V) to Vcc (+5V) needs close decoupling to circularise the data and clock related currents
Having DGND at the opposite side and end of the IC is really, really inconvenient for this decoupling to DGND.
Vcc to Vee5 on the other hand is fairly trivial.
For Vcc (+5V) and Vee15 (-15V) the previous analysis mainly holds, except AGND is not a key power supply node, but the Vcc (+5V) -> Vee15 (-15V) loop is most important
AGND doesn't seem to much, just provide some bias for circuitry referenced to Vee15 (-15V).
So we have to adjust the "optimum" decoupling and power supplies a little.
AGND and DGND can be separated by quite a substantial impedance, but the main current flow is always DGND.
My thoughts...
One 20V supply for Vcc -> Vee15 will handle audio AND inputs. A low impedance shunt "DC to light" is needed here, because it is a VERY MIXED UP mixed signal pin Vcc to DGND. Vee15 to DGND is also fairly critical due to the VHF glitches created by the DEM circuit.
A 10V shunt regulator from a 30V Supply (+/-15V) is entirely workable and circularises any signal current injected into +15V by the I/U conversion using Op-Amps.
In this case it is disrecommended to apply offset current cancellation, instead accept that the I/U conversion OPA has a significant positive DC on the output. This voltage and the DC current flowing in the I/U conversion resistor bias the OPA into Class A for the whole signal range. In fact, an extra pulldown to Vee5 or Vee15 may be used for emitter follower outputs to improve their open loop output impedance to absorb "glitches" passing into the output via the parallel capacitor on the I/U conversion resistor. The situation is less clearcut for RTO OPA's, which have collector outputs.
To make all shunts work correctly, we need to draw an extra bias of ~10mA from Vee15 to DGND.
So our +15V -> Vcc (+5V) shunt is 10V & passes an average 35mA (0.35W dissipation - TO-92 TL431 will do) and our VCC Shunt handles ~5mA / 5V.
DEM decoupling remains at Vee15, no change here.
A separate 5V supply between DGND and Vee5 supplies the digital part. This is FAIRLY uncritical, but still, watch common mode noise leakage.
So 20V or 30V DC @ ~ 50mA (depending on analogue circuit) for "analogue" and 5V @ 50mA for digital cover the TDA1541 stand alone plus analogue stages cover that part.
Really, a DIP32 case with AOLN/AORN and VCC-IN pin's added and DGND-IN (substrate!) at a pin next to inputs, DGND logic at a pin next to Vcc & Vee5 and AGND + Vee15 next to each other would have made life with the TDA1541 ever so much easier.
But unless we can send someone back in time to tell the guy's at Philips, I suspect we have to live with the IC as is.
Thor
I have redrawn the circuit for (I hope) more clarity on my guesses what happens inside the TDA1541:
The IDIN current source is modulated by clock and data inputs.
The IECL current source is also modulated by clock and data inputs. The modulation does not appear complementary to IDIN.
The IAREF current source is for now assumed DC, unless @lcsaszar can suggest different after checking with a high speed oscilloscope on his test setup.
The IDEM current source is for now assumed to be DEM logic only (not actual current generation) and more or less pure DC.
The IAOLN/IAOLP are the right channel signal current sources and are complementary, bit switches are located in the IAOLP lines which is "waste current" so the bipolar transistor base current error affects only the "waste" current IAORP, however IAOLP <> IAOLN.
The IAORN/IAORP are the right channel signal current sources and are complementary, bit switches are located in the IAORP lines which is "waste current" so the bipolar transistor base current error affects only the "waste" current IAORP, however IAORP <> IAORN.
There are some additional notes here on "balanced TDA1541".
Operating two TDA1541 as dual mono balanced DAC has one key drawback, there may be significant channel imbalance that must be addressed and pretty much doubled complexity (including I/U conversion) as second drawback.
However we have a few benefits.
1) The two AOXP currents cancel to within 1/2 LSB typically. So Vcc audio current modulation is minimised to 1/2LSB or a small fraction of feck all.
2) As data is always inverted, digital data based Vcc modulation is cancelled, BCK and WCK modulation remains. Also, data dependent edge leakage into the IC substrate is cancelled. BCK and WCK induced modulation remains. Data dependent jitter is de facto cancelled.
Additionally, latches, bit switches etc. also receive complementary data reducing any data dependent errors in the system
3) With a passive attenuation circuit before the TDA1541 complementary data cancels again the data dependent current and thus any possible data dependent jitter again is reduced.
So Dual Mono TDA1541 DAC does reduce some otherwise pernicious problems to next to nothing. It does so however at a price. Is that price worth paying?
Thor
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This very minor diff. of about 180 uA probably can be compensated with 2 X R from DEM 16, 17 pins to -15V.
?
I once set and measure 180 uA at DEM pins, cant remember the value of resistors... 🙁
?
I once set and measure 180 uA at DEM pins, cant remember the value of resistors... 🙁
After a test I have to disagree here. The DEM decoupling capacitors need a solid AC reference. AGND is as pure as it can be, but Vee15 is just a voltage regulator output with some inherent noise. This noise is passing through the capacitors, and modulates all 7 upper bit currents at the same time. In other words, there is zero PSRR. Compare my oscilloscope screen shots: first picture is capacitors referenced to -15 V, second picture is capacitors referenced to AGND.
Sure you can design a regulator having less noise (mine is a standard LM337T), but not less noise than the AGND.
1 vertical div = 0.9 mV, test signal: bit15 = 1, +/-1 LSB steps.
Attachments
First excellent work!
And thank you very much for empirically putting to the test and rejecting (or not) my theories.
We all owe you great thanks.
I agree with you and disagree with -15V as reference.
My original analysis was based a partial guesswork recreation of the internal schematic of the DEM/Analog part of the TDA1541, which we can now conclude is substantially inaccurate.
So my analysis was inaccurate regarding the actual TDA1541A. I should have realised the real state of affairs once it was clear that PSU current does not flow in AGND.
With AGND not a supply node for the DEM circuit it is obvious that it is the "quiet reference" all analogue is referenced to. So, yes, decoupling of DEM Filter to AGND. Analog Output filter capacitors to AGND.
Also, I think silent PSU GND to AGND and some decoupling from AGND to DGND (Resistor, Inductor?).
But where do we decouple AGND (and the noise from the DEM switching) to then?
Could you restore the 100R resistor and see what noise appears across the resistor this time?
Then, if there is noise or any spikes, use a 10nF Cap (100R & 10nF = 1uS = 160kHz) "probing" to all possible return nodes and see where the noise is lowest?
It might serve curiosity (and development) to make similar tests with 10R resistor's and 100nF capacitors in all power lines, if necessary using a crude 1nF/1kOhm high pass to only focus on noise from switching, clocks and DEM.
Thor
So, following on from the latest understanding we have gained with gratitude to @lcsaszar a provisional update to core and "simple" PSU:
TBD in the above schematic means "to be determined", meaning at this stage the best value (which may include nothing) is not known and needs more time.
Separate -5V from a separate wining using a LM317 (really, could be 7805, almost anything will worth there) with a positive regulator selected because of better availability of options and positive regulators generally performing better.
For the top we have a simple voltage regulator in the +line, series "Zener" shunts with a CCS in the bottom.
If there is enough extra unregulated voltage 7805 could also be used, both for CCS and Series Regulator (with Zener diode in GND line).
And of course nobody stops anyone from using incredibly complex "SuperMegaHyperRegulators" for series regulator and CCS.
Panasonic Os-Con on the output of all regulators.
Thor
If one asks I find subjectivly the 78xx reg, snapier than the LM317... whatever pre reg or main reg. And certainly a capacitance multiplier around a ziklai perhaps snappier than a 78xx if no big capacitor used after and just a decoupling for HF (mainly on -15V). Some even used BD140 without the resistor feedback at the output of the emiter follower and find it even better whatever the worse measurements. LM341 must be a little more filtered then.
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-15 Vdc is substrate potential in TDA15xx.
Once you reference DEM caps to substrate, you must change your (measurement) point of reference accordingly.
Great work 👍 @Icsaszar
Not to argue, but here the 317 is used as:
1) pre-regulator for a shunt chain of TL431, followed by a resistor and inductor, to establish predictable DAC operating conditions.
2) current sink for a shunt chain of TL431, followed by an inductor, to establish predictable DC operating conditions.
3) As 5V regulator for ECL(logic) which is effectively constant current draw and some input stage modulation.
Are we 100% sure on that? NPN can be isolated on the chip, enough for 15V. It's the only PNP transistors on the IC that bond collector to substrate (actually substrate = collector!)
If it bonds to -15V instead of DGND it has some interesting implications.
Thor
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