This thread is highly ambiguous:
TDA1541A reducing DNL
It is not clear how DEM was operated.
I found that with DEM sync and signal conditioned digital inputs measurable differences between different grades of TDA1541A largely disappeared.
Thor
It is maybe the wrong word?
Because if we take a look from the aspect of common points, they are:
1. Same input data format I2S to be transcribed into specific.
2. Same stopped clock in time
3. Same SRs.
4. Same datas order.
differences:
1. TDAs need a inverted MSB, AD and PCM not
2. TDAs LE rising edge to go to conversion, AD and PCM falling edge
3. BCK for AD has to be "out of phase", for TDA rising edge as data.
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Every thing is happening in the framework of fixed FS determine by I2S WS
With fixed bit count of 64 bits inside the frame of WS.
We cant made it slow or fast?
That is one sample rate simply, where is stored datas for left and right channel...
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I just want to emulate SAA and PMD formats but without oversampling...
BUT without moving or manipulating LE line from I2S origin. As the line from significant importance.
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74AUC16374 is good probably very useful for diskrete R2R because of integrated ENABLE.
But this is obsolete IC 🙁
And more important, it is very long IC with low width... That IC is very hard to put back and put innto the socket without damaging the pins or breaking up the IC 🙁
It is just for one time to be placed or soldered...
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I used available ICs from recent production. These 74F I accidentally find in local store as some leftovers...
The concept is to made adoptive design and with 4-5 jumpers to achieve desired configuration for specific dac.
You dont want to move LE. Rather move the DATA to LE. In TDAs datasheet noted for TS format that it coud go imeadetly to conversion after the last bit of data placed and after the last BCK. That time stated as 0s for TS format...
BUT we have 3/4 before the 16bit word, or 48bck cycles (with 16bit word length), "Blanc" digital space?
PMD100 in the datasheet doing opposite they moved the data and stopped clock to the left 5 BCK cycles after prior LE converted word before that LE. And Presence of BCK tells the system to load the datas. So they have "huge" "blanc"space after the word placed in register and waits for 16 bits 64-(5+16)= 43 BCKs time for that word set to conversion.
I think to put the word in between 2 LE cycles to give the system same time before and after the conversion.
BUT that could be changed within every direction, to the left or to te right tife to LE, with the same circuit. 🙂
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But we only need 2 X 16 Bit. All else is superfluous.
It is not. Active from TI, in stock at mouser.
Yes, of course.
Why? We can shift everything around to our hearts content.
Yes. This forces an unnecessary high BCK frequency. Why not follow this:
What is this "conversion" people keep mentioning? This is DAC and thus a simple state machine. It is not a SAR ADC where we want "quiet during conversion".
Following clocking data into the input shift register on BCK the LE edge updates the output latches (all CML/ECL).
The Latches directly drive the Bit Switches.
The DAC changes from one state to another state on each LE edge.
The Input Shift Registers change state with the BCK edge.
There is nothing else.
Thor
But it's dual TDA1541A pcb ?
What I posted as a 6 layers core pcb seems not to interrest many people, not sure what solution people would like to see here about pcb ?
1) Core pcb as I posted, according Thorsten's decoupling and Active DEM input whatever SMA or UF-L or even both as it is DIY ?
2) Bigger so more expensive to print PCB with the front end as well : I2S input, embeded Simultaneous mode with registers + attenuation plus its power supply
3) Modular core or 2 with header to stack different top pcb on which could be embeded the active corresponding DEM frequency related to the DEM caps values : could be simple two layer with different versions of DEM as 2 layers is not expensive.
4) A whole pcb : 2) + I/V discrete according Thorsten's shematic, + him authorisation to sell (royalties ?) here ? -So shortly said : a Blessed Insurection DAC for the DIY people ?
For Now, the 1) is finished with 6 layers with impedance matching and controlled return current loops, reliable if the new concept is working : Is this shematic has been already firered and sing or iss it yet just theory ?.
3) could be something interresting for DIY people to experiment several DEM frequencies by themselves
2) seems what people want mayybe to turn around to try several I/V Single Ended but get relaxed with thefront end, for instance : plug a JLSounds USB to I2S board if it works ok with the 45/48 K hz crystals on it (but it goes through a FGPA): stack is easy : put a header or two for the chineese board or for the JLSounds board.
I spent a lot of times already on th layouts but if continuing I would be glad to know what people and authors expect here and authorize or if there is any interrest. It seems hard to work at several on a same board and I thin due to the nigth and hours spent, one expect a little fee return, even symbolic : could eb start with a very low cost core to more expensive 2) 3) 4) etc options. Even some could realize their own I/V and make together something modular controlled by Zoran and/or Thorsten whom seem to have the technical lead ?
I am already communicating with Zoran. @ThorstenL : what would you like this project to be ? (PM ?)
Of course, it can be made by anybody, I just self proposed myself as a long time enthusiast and having experienced projects already that looks like that with that chip. But if there are already 20 ninjas in the background doing the same, it would be glad to know ! (pop corn + beer and look at the show from the seat instead !) 🙂
Anyway, I am open, let me know, all ! I started for myself and wanted to send a pcb to Thorsten and Zoran for humblle thanks to their contribution, but maybe even not needed at the end (verroboard and coppe/kapton tapes or selfmade pcb by everybody or opportunists of the GB Diyaudio section ?)
Poll or interrest list by members here or in a separate thread ?
Cheers
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The DNL compensation method elaborated in the other thread is for reducing the internal current divider inaccuracies. It in not intended for improving on the DEM oscillator and associated components. Especially not for compensating electrolytic capacitor leakage.
I found that the higher bit currents (bit 9 to bit 15, where bit 0 is the LSB and bit 15 is the MSB) deviate from their theoretical current value. This deviation is not related to the operation of DEM, which causes rather some ripple. In my experiments I used WS 44.1 kHz as DEM signal, with 330 nF decoupling capacitors. Higher frequency locked to BCK would be better. Worst is free running, I guess. The internal deviation of the individual bit currents from the theoretical value is related to the manufacturing process, and the chips (wafers?) are graded accordingly based on the DNL accuracy. Unfortunately I haven't got any S1 or S2, just R1, unmarked and made in Taiwan.
I have to add that the effect of DNL is not measurable at the full scale. Uncompensated and compensated bit errors measure the same THD, 0.001%! But at -60 dBFS and below it is totally different. H3 can be perfectly nulled out. The disadvantages of the compensation: increased component count, EMF sensitivity, need of special test generator (-60 dB dithered sine around each bit current DC level) and analyzer (FFT).
For now, I recommend a locked fDEM as high as it can go, good quality film decoupling capacitors, and the rest already written by Thor and others. For example, I have not found the power supply quality very important, I use plain 3-leg stabilizers. But I haven't got golden ears either .
I found that the higher bit currents (bit 9 to bit 15, where bit 0 is the LSB and bit 15 is the MSB) deviate from their theoretical current value. This deviation is not related to the operation of DEM, which causes rather some ripple. In my experiments I used WS 44.1 kHz as DEM signal, with 330 nF decoupling capacitors. Higher frequency locked to BCK would be better. Worst is free running, I guess. The internal deviation of the individual bit currents from the theoretical value is related to the manufacturing process, and the chips (wafers?) are graded accordingly based on the DNL accuracy. Unfortunately I haven't got any S1 or S2, just R1, unmarked and made in Taiwan.
I have to add that the effect of DNL is not measurable at the full scale. Uncompensated and compensated bit errors measure the same THD, 0.001%! But at -60 dBFS and below it is totally different. H3 can be perfectly nulled out. The disadvantages of the compensation: increased component count, EMF sensitivity, need of special test generator (-60 dB dithered sine around each bit current DC level) and analyzer (FFT).
For now, I recommend a locked fDEM as high as it can go, good quality film decoupling capacitors, and the rest already written by Thor and others. For example, I have not found the power supply quality very important, I use plain 3-leg stabilizers. But I haven't got golden ears either .
Yes but 176.4KHz will be at the DEM 16/17 pins external Fo only with 44.1KHz SR with dedicated BCK.
With higer Fo of sample rate external DEM will be higher
and DEM pins decoupling C will be remain for the 176.4Khz because of the fihed vaues of C calculated for 176KHz.
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So only when 44.1 SR the ratio from DEM pins (MSB to lower) will be in 1 : 1 with external DEM 16/17 input Fo
In other SR formats rise up it will be
1 : (2 N)
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This is interesting. Could the input lines be driven by PECL drivers directly (via 100R series resistor)? I considered TI's TB5D1M. Or perhaps an LVDS driver, like the SN65LVDS1DBVR or LVDS047 ?
Seems to me mostly pointless, as this stuff is very east to hardwired/3D/Veroboard.
My experience with modules is "don't".
If anything we need a complete solution, let's call it the "Gaucho DAC" containing:
1) TDA1541 Core with decoupling and power supplies for TDA1541
2) Socketing for I/U conversion (and analogue out?) option PCB's (plugin) which could include an Op-Amp Option, as I/U conversion needs to tightly integrate with 1) and should use the same PSU.
3) ECL Signal conditioning for LE/BCK/DL/DR/DEMP/DEMN including power supply
4) IIC2SIM conversion, and DEM Clock divider TDA1541 specific/only , I'm biased in favour of discretes. Includes power supplies (raw DC shared with 3)
5) MCK routing/selection using RF Relays and IIS clock/data routing with multiplexers/relays.
6) Clock Options for 44/48 clocks with suitable power supply (optional).
7) Footprints for "China Amanero Standard" digital input Modules.
8) Basic logic to make a unified sample rate indication, lock, signal...
Board should aggressively use high quality SMD and be fabable and PCBA capable from standard catalogues at places like JLCPCB for "generic parts.
The EXTREME OPPOSITE would be a Universal DAC board, with all the digital and PSU stuff "Universal" and small individual DAC & Analogue boards.
After totally dumping on the idea I might actually support it, as it can then have modules for many common IC's you find in old/cheap/broken CD-Players and allows any of them to be made into a "Killer DAC" simply.
Anything here from me is in the spirit of open source free.
Free as in "Free Speech" (which is not a right wing conspiracy but the foundation of our democracies) and "free beer" (which everyone likes).
We need some form of group where we can discuss minutiae, PM's here seem to not allow more than two people in a conversation.
Your call. I will give technical input and can help debug etc., but I'm not leading the project.
Thor
What you will gain using one expensive 48-pin chip instead of 2 chip 14/16-pin ones (164 or 595)?
Pin count? No.
PCB Space? No.
Money? No.
Alex.
The frequency of BCK could not be changed because of dte data bit is 1 BCK.
Actually we can extend the BCK time cycle BUT that will also be done with DATA each bit.
And that is not easy to do with logic gates.
It is a sort of opposite process of "return to zero"...
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So if we say double the BCK time it wil be time extention of each DATA bit by 2 times too. One Bit then will be 2*BCK.
And in that terms between LE pulses will be posibile to put 32 Bit. Wich is sufficient.
But there will be again "blanc" space with the word in that case 1/2 of
LE must remain the same because it is - sampling rate. we can not shrink or extend this value...
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It is not that easy like it sounds...
Yes...
Probably it will be additionay, harder to route the traces for PCB with condensed pins?
But imaggine putting that long and tiny iC into the socket? some pins will be probably damaged... Pulling out def. wil ruin half of pins...
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But maybe it will be good idea to incorporate somehow FIFO registers? But I am not that skilled and informed abou types. I tried some research but these chips are mostly obsolete... 🙁
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This is from vital importance for instance, for classical music with more intervals of quiet segments...
Sorry but forgive me to have some remarks on it?
The crucial problem, that will occur with probability of 0.8 minimum, with that complex modules merged into one PCB - that the board will not work, or that it will be some issues with this PCB... That is because of complexity, untested each module etc.
And then, it is again making a new PCB but without significantly decrease the probability of mallfunction.
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And that type of design is totally "closed". It is more for skilled and experienced engineers with praxis in same domain. Targeting new model on the market. But not for the diy community?
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It is better to be doubled speed to feed the USB/i2S inerface with and to have recklocking for max SR but that is independant module with own PS.
Why for chinese version when we have original? The cost is not to higher? And sound from XMOS devices are questionable and should be compared to amanero
That is already present on the amanero interface in the form of 4 bit word? It is posibile to have control with simple logic chip.
But if it is only to dyspaly the information on some dispaly - i dont see need for that. If it used to have some real purpose it is OK for me.
Anyway, sorry to using that word, do not have intention to oppose without arguments,
I think "opposite" 🙂 that the best way to have a motherboard with power suplies, all common/shared things. And DAC PCB has to be daughter board to come as module on that board. With stacked options for more DAC chips on it.
"Motherboard" with PS, super-capacitor or else,..
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this is a one of posibile examples of modular design
https://www.bramjacobse.nl/wordpress/?p=7175
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