Building the ultimate NOS DAC using TDA1541A

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#9,261
J_Perkins said:
Hello - beer for you, on me (life is good enough_watch space)
Click to expand...

Korb Kuhn Krub!

J_Perkins said:
I understand this, yet. If you want 384kHz - simdata mode input is necessary - all previous and not to shoot the somewhat rising SNR thread in the bollocks... so you have simdata input, or not?
Click to expand...

I will use IIS2SIM (AliExpress Chinese CPLD Board) in my build.

J_Perkins said:
You say you want 384k - no?.

_if so.. my question stands _ take BCK 32Fs /8 .., for fDEM. vs I2S BCK 64Fs /16 = same, same. Or same, Lion.
Click to expand...

The BCK from IIS2SIM cannot be assumed to be continous.

So it is unsuitable for DEM clocking.

If I was doing a PCB (set) I would use 74AUC74 for dividers, then TTL to PECL Translators for MCK & FDEM and a PECL Latch to reclock, drive the 330R with (say) 43R series resistors directly form the PECL Latch out, with 150R pulldown resistors on the PECL Latch outputs.

Reclocking and signal conditioning for the other lines (LE/BCK/DL/DR) would also use PECL Latches.

Thor
 
#9,262
ThorstenL said:
For a newly spun PCB, the C0G capacitors with explicit part numbers.
Click to expand...
Is that You are talking about, as some definite values of all decoupling power supplies and dem pins?
___________________________________________________________________________
01 - LE - no decoupling
02 - BCK - no decoupling
03 - DAL - no decoupling
04 - DAR - no decoupling
.
05 - AGND - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
06 - AOR - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)
.
07 / 24 - DEM LSB - 0.047uF/1206 to VEE1 (GCM31M5C1H473JA6L)
08 / 23 - DEM BIT6 - 0.047uF/1206 to VEE1 (GCM31M5C1H473JA6L)
09 / 22 - DEM BIT5 - 0.047uF/1206 to VEE1 (GCM31M5C1H473JA6L)
10 / 21 - DEM BIT4 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
11 / 20 - DEM BIT3 - 0.22uF/1206 to VEE1 (GRM31C5C1H224JE2L)
12 / 19 - DEM BIT2 - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
13 / 18 - DEM MSB - 2 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
.
14 - DGND - 0.47uF/1206 to VCC (GRM31C5C1E474JE1L)
15 - VEE1 (-15V) - 0.47uF/1206 to AGND (GRM31C5C1E474JE1L)
.
16 - DEM OSC1 - 1nF to 330R to 1nF to DEM OSC2
17 - DEM OSC2 - 1nF to 330R to 1nF to DEM OSC1
.
25 - AOL - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)
26 - VEE2 (-5V) - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
27 - FMT - link to VEE2
28 - VCC (+5V) - 4 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
- 0.47uF/1206 to DGND (GRM31C5C1E474JE1L)
___________________________________________________________________________

ThorstenL said:
The oscillator is not sinewave. Just look at the Schematic of it and the sawtooth waveform of the actual OSC pin's in free running operation.
Click to expand...
Yes main inside oscillator is always giving some sawtooth shaped signal... It is showing at the measurements...
ThorstenL said:
What do you hope to gain using a sinewave?
Click to expand...
Dont know. Nothing special. Just as a try and to measure and listen a bit? Because there is no any report about it.
ThorstenL said:
Don't tell me you also want to use a Tube LC oscillator to drive the DEM pins with a sinewave.
Click to expand...
No...
Whay You saying this? I dint wrote anything like?
 
#9,264
lcsaszar said:
I never understood why the MSB decoupling capacitor (and some bits below) should be bigger capacity than the rest.
Click to expand...

Because they have greater current ripple and lower effective switching frequencies.

lcsaszar said:
I have done extensive experiments with the decoupling pins ripple and sensitivity to "artifical" leakage current (using an adjustable current source) and I can say that all decoupling pins have the same sensitivity, same internal impedance, same ripple without capacitor, they are same in every aspect.
Click to expand...

So you are saying each pin carries the exact same sensitivity to current injection (that is 1uA into MSB same effect as 1uA into LSB)?

That contradicts all publications about the TDA1541.

Thor
 
#9,265
ThorstenL said:
Kind of. We can determine the minimum.

There is as such no maximum on capacitance. We see 100nF (standard CDP) to 680uF (MVAL) on the MSB.

We need to consider the worst case peak-peak ripple current, which is Iref / 4 * 10%.

We need the switching frequency and on each pin and the worst case ripple current.

In every group of 3 pins we have:

2 * I & Fdem / 2 on the MSB,
I & Fdem on the middle pin.
and I / 2 & Fdem / 2

Pin 3 is also the MSB in the next group of 3.

Or we have:

1 IrF - Group 0
1/4 IrF - Group 0
1/4 IrF - Group 0 / Group 1 MSB
1/16 IrF - Group 1
1/16 IrF - Group 1 / Group 2 MSB
1/64 IrF - Group 2
1/64 IrF - Group 2

So if we have a value of X for C bit 0 (MSB) and then minimum values of:

C0 = C0 / 1
C1 = C0 / 4
C2 = C0 / 4
C3 = C0 / 16
C4 = C0 / 16
C5 = C0 / 64
C6 = C0 / 64

New realisation, there is a geometric progression here, but it is C0 (MSB Cdem) that is critical and the geometric progression is not "each next C 1/2 the preceding value" even though this works at keeping the values above minimum.

The next challenge is to determine C0 min.

We need the variation from the ripple current (2.5% of 2mA worst case) cause less voltage variation across C0 (MSB Cdem) than 1/2 MSB respective to the nominal voltage across C0, which is ~7.5V.

So when does a PP current of 50uA produce 1/(2^17) or 0.000007629 of 7.5V or less?

When the impedance of the capacitor C0 at Fdem/2 is such that 50uA ripple produce 57uV or less ripple.

This suggest that the impedance of C0 should be < 1 Ohmm @ Fdem.

Let's assume Fdem = 176.4kHz.

Zc = 1 / (2 * PI() * F * C)

Zc = 1

thus

1 = 1 / (2 * PI() * F * C)

thus

2 * PI() * 176400 * C = 1

thus

C = 1 / 2 * PI()* 176400 (or Fdem)

C = 1 / 1108354

C = 0.9uF

A piece of evidence in support of the 1uF value:

View attachment 1350540

This circuit is from one of the fional TDA1541 designs ever done, a digital satellite radio tuner designed by Grundig for Philips, we see 1uF on MSB. We do not see 220nF on the next two though, but we often see all 220nF in upper end TDA1541 Designs.

If we use high frequency Fdem synchronised with WCK, we probably can relax the minimum value, as we always reliably average a whole cycle so the net ripple is ALWAYS zero and the remaining ripple is averaged out by the analogue stage.

If we do not relax requirements, we find (using standard values), for a minimum sample rate of 44.1kHz and Fdem = 4 X WCK

C0 = 1uF (or 0.94uF from 0.47uF C0G in parallel)
C1 = C2 = 270 or 220nF
C3 = C4 = 68nF
C5 = C6 = 15nF

In practice, based on the above I'd use for 176.4kHz Fdem (or minimum Fdem):

C0 = 2 X 470nF C0G // or 1uF Film // 100nF C0G
C1, C2 = 220nF C0G or 2 X 100nF //
C3,4,5,6 = 100nF C0G

Incidentally, for 60Hz it becomes 2650uF and for 120Hz we need 1325uF.

So for 120Hz:

C0 = 2 X 680uF KL 35V
C1,2 = 330uF/470uF KL 50V
C3,4 = 100uF KL 100V
C5,6 = 22uF KL 100V

Now all the above is based on the absolute worst case current ripple, which in real IC's likely affects at best 1 in 100 IC.

So lower values in practice are unlikely to cause big trouble, but I'd not go below half the theoretical minimum value, or a quarter if we use Fdem = 4 X WCK or integer multiples.

At the same time, as said, if it does not cause lower quality capacitors to be used, using larger values is not a problem.

Lastly, remember each DEM Filter capacitor pin has narrow glitches at Fdem that are about 50 - 100MHz equivalent frequency, so RF behaviour of these capacitors is important.

Thor
Click to expand...
Thank You very much that was very useful explanation.
So there could be relation with external DEM @ 16/17 pins and BIT DEM pins.
 
#9,266
lcsaszar said:
I never understood why the MSB decoupling capacitor (and some bits below) should be bigger capacity than the rest. I have done extensive experiments with the decoupling pins ripple and sensitivity to "artifical" leakage current (using an adjustable current source) and I can say that all decoupling pins have the same sensitivity, same internal impedance, same ripple without capacitor, they are same in every aspect.
Click to expand...
Yes ,I saw Your experiments covering a practical work and real world measurements. 🙂 I foun it very useful and not complicated to implement? Thanks 🙂
 
#9,267
ThorstenL said:
Korb Kuhn Krub!



I will use IIS2SIM (AliExpress Chinese CPLD Board) in my build.



The BCK from IIS2SIM cannot be assumed to be continous.

So it is unsuitable for DEM clocking.

If I was doing a PCB (set) I would use 74AUC74 for dividers, then TTL to PECL Translators for MCK & FDEM and a PECL Latch to reclock, drive the 330R with (say) 43R series resistors directly form the PECL Latch out, with 150R pulldown resistors on the PECL Latch outputs.

Reclocking and signal conditioning for the other lines (LE/BCK/DL/DR) would also use PECL Latches.

Thor
Click to expand...
Khaapn Khun
 
#9,268
Zoran said:
Is that You are talking about, as some definite values of all decoupling power supplies and dem pins?
___________________________________________________________________________
01 - LE - no decoupling
02 - BCK - no decoupling
03 - DAL - no decoupling
04 - DAR - no decoupling
.
05 - AGND - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
06 - AOR - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)
.
07 / 24 - DEM LSB - 0.047uF/1206 to VEE1 (GCM31M5C1H473JA6L)
08 / 23 - DEM BIT6 - 0.047uF/1206 to VEE1 (GCM31M5C1H473JA6L)
09 / 22 - DEM BIT5 - 0.047uF/1206 to VEE1 (GCM31M5C1H473JA6L)
10 / 21 - DEM BIT4 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
11 / 20 - DEM BIT3 - 0.22uF/1206 to VEE1 (GRM31C5C1H224JE2L)
12 / 19 - DEM BIT2 - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
13 / 18 - DEM MSB - 2 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
.
14 - DGND - 0.47uF/1206 to VCC (GRM31C5C1E474JE1L)
15 - VEE1 (-15V) - 0.47uF/1206 to AGND (GRM31C5C1E474JE1L)
.
16 - DEM OSC1 - 1nF to 330R to 1nF to DEM OSC2
17 - DEM OSC2 - 1nF to 330R to 1nF to DEM OSC1
.
25 - AOL - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)
26 - VEE2 (-5V) - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
27 - FMT - link to VEE2
28 - VCC (+5V) - 4 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
- 0.47uF/1206 to DGND (GRM31C5C1E474JE1L)
___________________________________________________________________________
Click to expand...

Adjusted on latest analysis:
___________________________________________________________________________
01 - LE - no decoupling
02 - BCK - no decoupling
03 - DAL - no decoupling
04 - DAR - no decoupling

05 - AGND - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
06 - AOR - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)

07 / 24 - DEM LSB - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
08 / 23 - DEM BIT6 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
09 / 22 - DEM BIT5 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
10 / 21 - DEM BIT4 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
11 / 20 - DEM BIT3 - 0.22uF/1206 to VEE1 (GRM31C5C1H224JE2L)
12 / 19 - DEM BIT2 - 0.22uF/1206 to VEE1 (GRM31C5C1H224JE2L)
13 / 18 - DEM MSB - 2 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
.
14 - DGND - 0.47uF/1206 to VCC (GRM31C5C1E474JE1L)
15 - VEE1 (-15V) - 0.47uF/1206 to AGND (GRM31C5C1E474JE1L)
.
16 - DEM OSC1 - 1nF to 330R to 1nF to DEM OSC2
17 - DEM OSC2 - 1nF to 330R to 1nF to DEM OSC1
.
25 - AOL - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)
26 - VEE2 (-5V) - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
27 - FMT - link to VEE2
28 - VCC (+5V) - 4 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
- 0.47uF/1206 to DGND (GRM31C5C1E474JE1L)
___________________________________________________________________________

Zoran said:
Yes main inside oscillator is always giving some sawtooth shaped signal... It is showing at the measurements...
Click to expand...

Well, that is on the RC. What you see is a more or less constant current ramp to a threshold, at which point the circuit "flips" rapidly (the straight vertical line) switching one side's transistor off and the other on.
A sinewave will not change this behaviour, but will have a slower transition at the critical switching point and thus more uncertainty.

Zoran said:
Dont know. Nothing special. Just as a try and to measure and listen a bit? Because there is no any report about it.
Click to expand...

Your call. No point IMNSHO.

Zoran said:
No...
Whay You saying this? I dint wrote anything like?
Click to expand...

No, you did not write this. But there are some ideas like tis making their rounds:

SW1X DAC III – The Legendary Classic

  • Pure NOS (Non oversampling – zero digital domain filtering) R2R Design
  • Selected and Harmonically Matched Component & Material Quality
  • Anode Follower, Zero Negative Feedback, Single Ended, Class A, RC (resistive loaded, capacitive de-coupled) Valve Amplification Topology
  • 6N6P Double Triode Valve Output Stage, 6X5 Indirectly Heated or Directly Heated 5Y3 (SPX version) Valve rectified CLC (choke filtered) Power Supply
  • Dynamic Element Matching (DEM) of the TDA1541 is powered by an asynchronous E180F Valve Clock with EAA91 Valve rectified Power Supply
  • Active I/V conversion via a single specially selected transistor (with less than 10 Ohm input impedance) with the shortest signal path directly connected to the tube grid
  • Circuit is wired with of a specially selected copper (single strand or Litz)
  • Discrete Transistor Shunt Voltage Regulated Power Supplies for the TDA1541, SPDIF receiver and active I/V conversion
  • 3 (4 x on VSB version) x EI core Mains Transformers & 2 x Chokes
Click to expand...

Can you say "Hai Ente"?

1725017565956.png


Thor
 
Last edited:
#9,269
ThorstenL said:
So you are saying each pin carries the exact same sensitivity to current injection (that is 1uA into MSB same effect as 1uA into LSB)?
Click to expand...
It is rather in the nA range. Of course, each bit has progressively increasing current, -2 mA for MSB, -1 mA for the next lower bit and so on until about 61 nA for the LSB.
What I am talking about: we can deviate each bit current by the same external "leakage" current for the same Differential Linearity Error, expressed in LSB current fraction. This means the sensitivity of each bit decoupling pin is the same. A given leakage current or ripple causes the same output current error or variation in each decoupling pins.
 
#9,270
lcsaszar said:
It is rather in the nA range. Of course, each bit has progressively increasing current, -2 mA for MSB, -1 mA for the next lower bit and so on until about 61 nA for the LSB.
Click to expand...

Ok, so here we agree.

lcsaszar said:
What I am talking about: we can deviate each bit current by the same external "leakage" current for the same Differential Linearity Error, expressed in LSB current fraction. This means the sensitivity of each bit decoupling pin is the same. A given leakage current or ripple causes the same output current error or variation in each decoupling pins.
Click to expand...

Yes, a given voltage ripple should cause the same output disturbance.

But the current ripple is a fraction of the reference current and occurs at varying frequencies.

If we posit an identical voltage deviation across Cdem with varying current and frequency we get different minimum capacitor values to satisfy a given voltage deviation limit.

Thor
 
#9,272
@diyiggy Hi It is I2S to TDA AD and PCM series of DACs. For all word bit length. Stop BCK is also on.
(Can be used even as base for diskrete R2R dac up to 32bit.)
In this version DATA and stopped BCK are placed in the "middle" between the LE pulses. But that can be changed to move the data and BCK left or rifght to LE.
(For instance PND100 word starting 5 bits "from left".)
Baring in mind that conversion take place when LE is active, on DATA stored before this LE pulse.
LE for TDAs is within rising edge, and for the AD and PCM is on the fallen edge of pulse, That is why they are not in the same "place"
Best results are obtained in the sim with 74F and 74AHC series.
cheers.
Zoran_I2S_TDA_AD_PCM_MIDDLE.jpg


Zoran_I2S_TDA_AD_PCM_MIDDLE_time.jpg
 
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#9,274
Brijac said:
Isn't it in the end much better to use CI from lcsaszar real world experiment? Little bit more complex, but it's tested and works good.
Click to expand...

What do you want use it for?

After serious consideration I will not use or recommend low speed DEM with leaky electrochemical condenser's that need external compensation, all which will be temperature and aging dependent.

If using low leakage capacitors and 4 X WCK DEM there is no issue to fix.

Thor
 
#9,276
ThorstenL said:
What do you want use it for?

After serious consideration I will not use or recommend low speed DEM with leaky electrochemical condenser's that need external compensation, all which will be temperature and aging dependent.

If using low leakage capacitors and 4 X WCK DEM there is no issue to fix.

Thor
Click to expand...

He wasn't using 100uf eg. 50hz mod. And still his measurements show significantly better results.
 
#9,278
Zoran said:
@diyiggy Hi It is I2S to TDA AD and PCM series of DACs. For all word bit length. Stop BCK is also on.
(Can be used even as base for diskrete R2R dac up to 32bit.)
In this version DATA and stopped BCK are placed in the "middle" between the LE pulses. But that can be changed to move the data and BCK left or rifght to LE.
(For instance PND100 word starting 5 bits "from left".)
Baring in mind that conversion take place when LE is active, on DATA stored before this LE pulse.
LE for TDAs is within rising edge, and for the AD and PCM is on the fallen edge of pulse, That is why they are not in the same "place"
Best results are obtained in the sim with 74F and 74AHC series.
cheers.
View attachment 1350551

View attachment 1350552
Click to expand...

Interesting. This illustrates the point I always make about making things "universal" instead of dedicated to a single function.

I suggest you consider replacing the 74XXX164 with 74AUC16374, which cut's the IC count dramatically. Using inverters in series is a bit dodgy as reliable delay, RC is preferred if using CMOS logic (74F is different).

But if we make a dedicated design for TDA1541, I would use a pair of 16374 to hold the data from the IIS bus (top 16 MSB only L/R) as serial to parallel conversion.

Then transfer this data into a second pair 16374 configured as parallel in serial out that clock out the data at BCK = 16 X WCK to DL/DR.

The LE pulse comes after bit 16 and also latches new data into the output shift registers.

BCK to TDA1451 is continuous as 16 X WCK. Everything becomes simple and slow.

Stopped clock in SIM is not useful IMNSHO.

Thor
 
#9,279
ThorstenL said:
Adjusted on latest analysis:
___________________________________________________________________________
01 - LE - no decoupling
02 - BCK - no decoupling
03 - DAL - no decoupling
04 - DAR - no decoupling

05 - AGND - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
06 - AOR - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)

07 / 24 - DEM LSB - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
08 / 23 - DEM BIT6 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
09 / 22 - DEM BIT5 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
10 / 21 - DEM BIT4 - 0.1uF/1206 to VEE1 (GCM31C5C1H104JA16K)
11 / 20 - DEM BIT3 - 0.22uF/1206 to VEE1 (GRM31C5C1H224JE2L)
12 / 19 - DEM BIT2 - 0.22uF/1206 to VEE1 (GRM31C5C1H224JE2L)
13 / 18 - DEM MSB - 2 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
.
14 - DGND - 0.47uF/1206 to VCC (GRM31C5C1E474JE1L)
15 - VEE1 (-15V) - 0.47uF/1206 to AGND (GRM31C5C1E474JE1L)
.
16 - DEM OSC1 - 1nF to 330R to 1nF to DEM OSC2
17 - DEM OSC2 - 1nF to 330R to 1nF to DEM OSC1
.
25 - AOL - 0.01uF/1206 to VEE1 (GRM3195C1E103JA1D)
26 - VEE2 (-5V) - 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
27 - FMT - link to VEE2
28 - VCC (+5V) - 4 X 0.47uF/1206 to VEE1 (GRM31C5C1E474JE1L)
- 0.47uF/1206 to DGND (GRM31C5C1E474JE1L)
___________________________________________________________________________
Click to expand...
thanks
 
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