"It's not expensive, i don't really think thats the issue, some opamps used cost more. Custom wound ones are better, much much better. You can check vendor topic by bisesik. It costs hefty amount more than the ones you use, but are miles apart in quality."
How do you know? Have you actually used the same Sowter one?
Is the one you mentioned biflar wound?
I don't mind which works best: you just have to like the results. My budget was stretched buying the Sowter ones but 8years on and I am still using them.
(my reference CD player is an Arcam FMJCD23 with a dCS Ringdac & PMD200 HDCD filter - its the best CD player I have heard, followed by a Pink Triangle Ordinal dac using the TDA1547 'dac 7' but I still prefer the good old TDA1541a)
How do you know? Have you actually used the same Sowter one?
Is the one you mentioned biflar wound?
I don't mind which works best: you just have to like the results. My budget was stretched buying the Sowter ones but 8years on and I am still using them.
(my reference CD player is an Arcam FMJCD23 with a dCS Ringdac & PMD200 HDCD filter - its the best CD player I have heard, followed by a Pink Triangle Ordinal dac using the TDA1547 'dac 7' but I still prefer the good old TDA1541a)
Pink Triangle Ordinal !!!!!! wow this was when I didn't have grey hair. Lol
So you haven't personally heard a 9545/1465 with dual balanced 1541s, (or any other current output dacs) therfore your comments are opinion not based on first hand experience.
I'm not defending my purchase, I am defending Sowter's right to fair treatment and respect. I have never ever claimed using them is in any way superior to any other I.V stage.
It needs to be 4 X WS IF using high frequency DEM clocks and low(ish) value DEM Filter capacitors.
This is because of the way the DEM current splitting works. Also, given the timing needs for the DEM circuit is pretty tight, the original oscillator is a bit too jittery.
In principle, running 4 X WS should allow to not use any DEM Filter capacitors, but the results of doing so seem interesting.
No, that is a "side benefit".
They are there to store the averaged voltage that causes the precise bit current to flow.
The switching current splitter sends a current into this structure (MSB's):
This current has actually 4 individual currents as components which may vary by as much as +/-5%.
The current causes voltage to be dropped across the "filter" resistor.
The resistance of this resistor and the capacitor form a moving average filter.
But the circuit composed of the cascoded Darlington transistor, resistor and Cext form a CCS in their own right:
If we replace Cext with a DC source we have a static CCS. This one is dynamic and the current passing is the moving the current "Ibit". Now Ibit is created using a switched "Dynamic Element Matching" system that uses averaging to eliminate errors.
Essentially the actual operation of the DEM circuit is that short time highly stable Transistor/Resistor/Capacitor current source that tracks the moving average of the current supplied by the switched current splitter:
It is not that simple. Use higher value capacitors with VERY low leakage. Low leakage is not as easy as it seems. Check this for details:
TDA1541(A) Dynamic-Element-Matching Slowed Downhttps://www.mvaudiolabs.com/digital/tda1541a-dynamic-element-matching-slowed-down/
Also, using the build in oscillator not synchronised to an external clock leaves timing errors that translate into level errors.
The combination of these errors are sufficient to trigger this thread to fix the problems introduced by fitting large value, leaking capacitors and slowing down the oscillator:
TDA1541A reducing DNL
If instead using Film Capacitors and a high DEM Frequency that is 50% duty cycle and low jitter the problems with these issues disappear and we are back at the "designed in" performance of the TDA1541.
So, it is important to consider the tradeoff's with different approaches.
I am not saying that there is just ONE option, but rather that each option comes with challenges and limitations and these need to be considered.
Incorrect, the DCR is high, the AC Impedance is low, equal to appx. the resistor R which is between 1.6K on the MSB's. The emitter Impedance of BJT is 26 Ohm / Current (in mA).
Well, may I suggest:
TDA1541(A) Dynamic-Element-Matching Demystified
Sound decoupling caps TDA1541a
Dynamic Element Matching modificaties
Grundig DEM Modifictions 176.4 vs 705.6 Khz
220nF @ 44.1khz are a bit low for MSB.
Note, you can use any DEM frequency you like (< 6MHz appx, the limit of the transistors and circuitry in the TDA1541).
You can omit DEM filter capacitors. You can run the DEM oscillator stopped
You can make 14 precise Voltage sources with suitable thermal tracking to the TDA1541 die temperature and feed the DEM Pin's with low impedance voltages (must handle a few mA DC offset) with the DEM oscillator stopped.
It will work. How well, depends.
Running Fdem at 44.1KHz will create idle tones at 22.05Kz and 11.025KHz at levels that depend mainly on the filter capacitor value on the MSB filter.
You can do whatever you like. You can even get an ESS DAC Chip and use an AD797 as I/U converter and feed the IC with a jittery 125MHz clock and feed it with a high jitter source asynchronous to this and listen to the result. Nobdy is telling you what to do.
I stated that Fdem has a few technical strictures, IF we want to avoid idle tones within the Audio Range and get optimum linearity.
These are:
Fdem / 2 <= 20Hz
Fdem / 4 >= 20kHz
realistically we can probably relax this requirement to:
Fdem / 2 <= 40Hz
Fdem / 4 >= 15kHz
Not that it does much really.
Other frequencies will create idle tones that depend the match of each current source in the specific set feeding the specific pin and the capacitance of the capacitor and the fixed general DEM frequency switching glitches.
From John Brown, DEM Pin without capacitor and DEM oscillator
DEM system, observe the stepped waveforms similar to the oscilloscope trace
Now given that we have 4 different currents for each complete DEM cycle stating that Fdem should be an integer multiple of WCK and at least 4 X WCK so that all 4 states are used for a single sample.
This way any error folds back to DC. And as long as our capacitors have negligible leakage current (e.g. C0G ceramic or Film types) the DC error asymptotically approaches zero over time (though to get absolutely zero requires infinite time).
Mind you, I showed the Graphics earlier in the thread, where I made said assertions, to illustrate exactly why I made them. I already repeated them more than once. I would appreciate if you could not ask me to explain the same thing over and over again.
Above are my arguments why Fdem must be either < 40Hz (< 80Hz for the relaxed requirements) or 80kHz (60kHz relaced requirements) unless we want tolerate distinct idle tones within the audible range and why unless we use very large value DEM filter capacitors we want a DEM frequency of WCK * 4 which also is the integer multiple of WCK if greater than WCK * 4.
Thor
Yes, 1980s I think. It was a step up compared to the usual crop of mid range CD players.
I only recently found out what Arcam meant with their FMJ designated high end products (Full Metal Jacket, referring to the heavy metal chassis)
Most CPLD's or FPGA's will have around 100pS jitter even if using on chip relocking. There are often output settings that can be used to optimise this, but clocking on FPGA/CPLD is NDFG.
Complex topic. There is a specific long discontinued CPLD that it seems is much better on clocking than modern types. I'm not going to venture suggestion.
But every extra CMOS inverter in series with something will add what Ed Meitner calls LIM. It amounts to ground/supply bounce and current spikes on switching. CMOS logic is really quite a nightmare.
As long as we use non-saturating bipolar logic (74AS, 74F, 74ALS, 74LS depending on required speed, or ECL) or special CMOS logic designed explicitly to control these problem (e.g. 74AUP/74AUC ) this can be minimised, but no CPLD or FPGA known to me uses such designs. The cores usually run on 1.2V or 1.8V which is good, but the I/O and the routing logic runs at Vi/o and uses many crosspoint switches and buffers.
Clocktree design for FPGA's is quite a bit of a black art. It gives me major headaches.
Thor
#me2
Non of the fundamentals changed, except for my BBFOTO that AGND & -15V and DGND and +5V are fundamentally separate supplies and that the true "common" of the whole DEM current generation is -15V, not AGND.
No real consenus.
The current fad is very large value electrolytic capacitors and running DEM at 100 or 50Hz.
What are FIFO buffers for? USB now has very low jitter. SPDIF with WM8805 in practice often ends up < 10pS RMS jitter.
Integrating a computer into a DAC is IMNSHO asking for trouble. Plus it needs changing every 2 years.
Simultaneous mode allows 384kHz or allows "stopped clock" operation at lower frequencies.
I think the "stopped clock" helps where the whole layout is suboptimal because of blindly following datasheets, the very low DEM frequencies fall into the same category.
In various recent posts here I provided a lot of information and links to "further reading". Feel free to peruse these.
If you ask me, pointless, UNLESS you are looking for more bit's than 16 Bit.
Matching from IC to IC, even on the last "Taiwan" chips is not great.
A single TDA1541 will give 110dB SNR at (static) digital silence.
Analogue Output Linearity depends on the Analogue stage, DEM Clock stability and DEM Filter capacitor leakage to a degree that multiple units in parallel or balanced are unlikely to provide direct improvements in this area.
Each have specific uses.
Balanced is useful with transformers as analogue stage, as we can double allowable signal levels. But quite a bit of channel imbalance is possible.
Interpolated means usable sample rate doubles. When playing 44.1 Non-Oversampled individual DAC's run at 22.05kHz and 768kHz sample rate Audio can be played. No real other benefit and you need matched DAC Chip's or trim.
Parallel - no benefit for 16 Bit audio.
Using (say) 8pcs in parallel will give ~119dB SNR and thus allows us to use a 9th TDA1541 for the lower 16 LSB's with a suitable pad on the output to get the current's to match (something having 8 X current for the upper 16 Bit also helps) gives us a true 32Bit DAC with TDA1541 with ~ 119dB SNR/DNR.
AMR has (had?) ~1,000 Taiwan TDA1541 in stock in 2018, no idea what happened since. The above concept would have made a one off series of 100pcs of DAC's at a price of like 100k USD. Whatever. Something like that. Multi box Stack, all voltage tube rectified and regulated, including TDA1541's etc. Totally crazy.
Thor
I had them before. My biggest issue that these force balanced mode (no way to use SE) and need resistors that are still too high.
There are much better choices of transformers, you want 1:30 minimum step-up, 1:40 is even better. Reichenbach (Cinemag) has suitable choices.
Of course, next to these Sowter's are dirt cheap.
Thor
I think NO... Because I will end up with only 192K max because of the MCK value was 22.xxx 24.xxx MHz 🙁
With max sampling rate, with given clock oscilators, BCK = MCK so the recklocking is not posibile for BCK line)
I Just try to find max SR of TDA1540 and in 16bit for TDA1541A with the I2S/TS cpld board.
@ThorstenL thanks for the BJT IV.
+ Notes about power supply decoupling and grounds - very useful to me.
.
Very very good perorming. I just made quick probe and a bit rearrange circuit, just positions of few BJTs. Current is a bit higher. Zero offset on Iout pin can be adjusted (with R4 trim pot), Very low distortion,-160db floor, and 1Vp-p is more than enough. There is no Fr dips and it can go "infinite" high. Circuit well behave even with lower Riv (which is the issue with most BJT IV stages). So the tube gain stage can be added... Off-course probably has to be checked by someone with more knoledge on BJTs.
+ Notes about power supply decoupling and grounds - very useful to me.
.
Very very good perorming. I just made quick probe and a bit rearrange circuit, just positions of few BJTs. Current is a bit higher. Zero offset on Iout pin can be adjusted (with R4 trim pot), Very low distortion,-160db floor, and 1Vp-p is more than enough. There is no Fr dips and it can go "infinite" high. Circuit well behave even with lower Riv (which is the issue with most BJT IV stages). So the tube gain stage can be added... Off-course probably has to be checked by someone with more knoledge on BJTs.
Use a single. More than one doesn't really help with anything.
Don't use transformers direct off the Chip. The ones that really work well, have such high output impedance, you need to add buffers, so all the fake "simplicity" is out of the window. For resistor I/U conversion we really like < 5R.
TDA1541 I/V Resistor Selection
Use a current conveyor with < 1 Ohm input impedance, I/U conversion resistor to +5V. Make it part of the TDA1541 circuit, so you get a sensible voltage output.
With 250R/353mV (as shown) a 1:5 transformer gives 1.76V from 6.25k source impedance, marginal but usable. Multiple suitable items exist, of course a DC blocker will be needed.
Use 4 X WCK DEM Clock, after looking around and actually simulating the oscillator inside the TDA1541 I'd go with Tubee's circuit. It can be tuned to have reliable lock without throwing noise onto the TDA1541 die. Don't stop the DEM oscillator (2k2 resistor from 16/17 to -15V) just force it into phase lock.
Use the lowest voltage swing possible on inputs (including DEM Oscillator), slew rate limited, ideally 250mV P-P.
These days I'd use 74AUC16374 etc. as final reclocker before the attenuator, as going ECL is too much hassle. Otherwise ECL Latches, ECL Frequency dividers and ECL Clocks (with Outputs to CMOS for USB etc.), essentially a consequent application of:
Paul Winser - CD Jitter (ECL Clock)
Optimise power supplies for DEM (not REALLY analogue) and Digital. Consider relevant current loops. Do not link DGND and AGND near the IC.
Optimise PCB Layout. In my books that get's us to 6 Layers, -15V & AGND planes below PCB, +5V and DGND planes above PCB, two spare layers for routing, system ground plane etc.
My thinking so far. A possible PCB project with hardware I2S to SIM converter is being discussed that might follow the above, with added options for 50/60Hz DEM clock.
Thor
Should be fine.
At 384kHz and 16 Bit BCK output should be 6.144 MHz which is within the TDA1541 limits and if you have 6.144MHz it's easily reclocked with 512X clocks.
Only LE and DEM need reclocking anyway. Rest I'd directly use the CPLD loutput.
!!!! NOOOO.
Thor
Try MPSA18 for the NPN.
PNP, look for the fastest you can get at the current that is running.
Thor
Well:
| Distortion (primaries connected in series, source impedance 50Ω ): | < 0.5% @ -8 dBU, 50 Hz |
So with 4 : 32 (or 1:8) we can only handle 310mV @ 50Hz for 0.5% THD (mostly H3) and only 77.5mV @ 25Hz for 0.5% THD. Connected 1:32 ~20mV/25Hz will produce 0.5% THD.
I'm sure there will be sound coming out. The extra "Aphex Big Bottom" like distortion may sound better than a clean option, especially if the system has speakers with limited LF extension.
Me? Thank you but no thank you.
Thor
384KHz x 64 = 24.576MHz
I am ususalu using 2 x flip flop in series for recklocking one digiral line. That giving a one period of delay of MCK that doing "recklock"
So if the all lines does not treat with same recklocking, one without will be "prior" these recklocked for 1 MCK cycle.
So if we want to avoid delay between BCK and DATA we have to recklock booth.
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Yup, It is not the price, it is just it is known as not the best solution. It is known for years. Nothing new. Yup for Bisesik ; Tribute; etc !
And what to say to the talk of : it is passive, so no active, so it is betterbecause no altered blah ! We are in the magical thinnking there ! Do they have not active device as well after, btw ?!
It is certainly not bad, but to said people are closed mind as if they didn't know is of a same shortcut thinking imho !
But if you use Grunding mode NOS, i.e. WS=DEM sync = 44.1 K hz ; then it is divided after in the chip per 4 and the noise is rigth in the audio passband.
So with the 0.220 uF film DEMx14 filtering, you measured no more noise ?Or at least different disto spectra ?
It interresting to notice you like it best with the ears after a listening test... It is a great information, I wonder why this post is not more talked !