We will have to agree to disagree.
Correct. Hence I prefer to avoid them.
The only way to get intersample oblvers is to use a badly designed digital filter. The correct mitigation strategy is to not use the filter. Which is what we do in this thread.
It would also help a lot of recording engineers didn't use overs to make things louder, most good ADC's have a soft clipper option for the top 6dB or so, even better a tape emulator can crush tops by easily over 9dB and adds LF harmonics, that overall sound much better than digital clipping.
But that's a different thread for very different fora.
I seriously considered this as well, but the question is: "What if the 'send low level noise when idle to keep device awake' option in settings is checked?
After reverse-engineering the XMOS supplied code (more comments next time, please) and already having a single programmable clock with the necessary setup to allow external WCK sync l, I figured reusing all this and most of the USB Subsystem to make I2S and SPDIF/AES-ENU etc. bitperfect, low jitter asynchronous was logical.
Thor
Does it make sense to divide XO clocks before using it for reclocking? Considering fast flip-flops like 74AUC.
It is claimed to reduce phase noise energy by 6db per /2. I'm going to use NDK 45/49MHz XOs, so I have some headroom. Does it worth it?
https://www.mvaudiolabs.com/digital/tda1541a-reference-dac/#tick-tock
It is claimed to reduce phase noise energy by 6db per /2. I'm going to use NDK 45/49MHz XOs, so I have some headroom. Does it worth it?
https://www.mvaudiolabs.com/digital/tda1541a-reference-dac/#tick-tock
Yes. BUT as they are differential, if device A has a connection to mains earth and device B has a connection to mains earth (and each has some leakage to earth) we can remove the GND link without problem. USB2 can easily handle a few 100mV common mode noise.
To make it safe, let's use 100R/1nF to still remain a link for RF purposes and a pair of anti-parallel diodes to act as protection. Plus, let's add a bypass switch.
I designed this into the 99 USD iFi USB power supply and it worked great to kill all sorts of USB earth/Ground loop problems.
Yes, shall we use "ground lifted" for the case where there is no "hard" ground connection via the USB cable?
No, non of them inherently isolate Vbus & GND ON CHIP.
They allow such isolation to be implemented, but it is not an inherent function of the IC.
Yes, DC-DC ideally sinewave - push-pull. Switchers are a serious effort to quieten.
Me.
Thor
Depends. If you can make sure that the actual timing uncertainty is reduced?
Say we have a given -110dBc @ 10Hz phase noise for our clock and divide by 2 and now have -115dBc @ 10Hz.
Have we actually reduced the absolute timing uncertainty at the re-clocker or increased it? (Hint, trick question).
Thor
Yes, but this is not galvanic isolation,. because you eliminate GND wire in USB cable, but not GND connection.
I don't know, but what I consider "galvanic isolation" is if you connect a DVM between two opposite sides and get infinite resistance (at least at DC).
USB isolators isolate two opposite sides, how you provide Vcc to the second side is your problem. The main goal, is that GND1, VCC1 are isolated from GND2, VCC2.
Alex.
Gotcha. it stays the same + intrinsic jitter of the flip-flop. Correct me if i'm wrong.
So the answer is no 🙂
Correct. In practice and in my experience the difference between this and full galvanic isolation is small, even smaller if using a re-driver before the USB device (which brings us in line with the isolator electrically).
Correct. But that is still down to implementing the IC.
If someone connects both sides grounds and Vbus together the IC still galvanically isolates the data lines, but the USB source and Sink are not isolated (basically the opposite of the above case where there is no GND/Vbus connection but uninsulated data lines.
And yes, I have seen such "isolators".
Only if the engineer implementing the IC chooses to separate the two supplies, instead of saving a few bob.
Thor
Interesting.
Just recently I take advantage from the feeding the signal to the cathode (low impedance), and put a passive CLC filter to make the low pass filtering, show as active here in this option.
The low impedance of both sides using cathode as the buffer input permits a relatively low impedance CLC.
The good of passive filtering is that it supports a lot of rise time from the DAC, if it wants hehe
Good also if the DAC have a lot or HF gargabe.
The bad, is the mains noise signal picking.
The THD with 2V.... interesting....
0.1% distortion? Exactly that I achieved with my "not-so-ultimate" TDA DAC, but with submini tubes I mention some posts ago:
-60dB:
Better tube (ones with less Island effect) will have less distortion, and almost no 3H at these levels.
Years ago, when I built the humble 2-layer board for the TDA, I locally bypassed every supply and bit decoup pins directly to the ground plane below the TDA, with some 1nF caps. I dunno it it is worst than bypassing with only one cap in the board (the normal situation), but I leaved it anyway. Time flies, and I read about the separated current returns for bit decoup caps, hence the interest of all people here for 4-layer implementation.
seems Mouser has 4000 sn74F74DR (soic version for whom prefering), one of the free choice became end of life statut.
It depends of a use case.
For me, I prefer to use isolation on I2S rather than on USB. But this is only possible for the devices I develop.
As a general solution, for use with others where a USB isolator should be used, in my isolator I use DC-DC (5v-5v), but external 5V is also available (internal DC-DC is completely disconnected to avoid noise).
Alex.
Also J-K double F-F can be used as divider, maybe better
74F109
https://www.mouser.com/ds/2/302/74f109-288394.pdf
Hi I found the notes of measured datas on TDA1540 (10 DEM pins Cs, 14bit) long time ago. With -18V negative supply following the DEM pins:
.
TDA1540 (plastic version)
DEM pins Vdc measured with -18V power supply
pin -Vdc Cdem
12 -9.25V (470nF)
13 -6.93V (220nF)
14 -7.1V (100nF)
18 -4.84V (47nF)
19 -4.69V (22nF)
20 -3.09V (10nF)
21 -3.03V (10nF)
23 -2.68V (10nF)
24 -2.64V (10nF)
25 -2.38V (10nF)
.
Corrected PDFs for DEM Capacitors for TDA1541A and TDA1540
.
.
TDA1540 (plastic version)
DEM pins Vdc measured with -18V power supply
pin -Vdc Cdem
12 -9.25V (470nF)
13 -6.93V (220nF)
14 -7.1V (100nF)
18 -4.84V (47nF)
19 -4.69V (22nF)
20 -3.09V (10nF)
21 -3.03V (10nF)
23 -2.68V (10nF)
24 -2.64V (10nF)
25 -2.38V (10nF)
.
Corrected PDFs for DEM Capacitors for TDA1541A and TDA1540
.
It is not easy finding a tube with a cathode impedance in the 10's of Ohm.
One might use something like several J-Fet's (say 3pcs J310 at 7mA each for ~30R input impedance) cascoded with a triode that is happy at 20mA (say 5687)
There are other tubes that lower HD and we could use topologies that cancel H2, but other than bragging numbers, what's the point?
Probably a good idea.
Thor
BTW, what will better for higher capacity (let say 5-20uF) at the digital power - X7 ceramic or tantalum, both 0805 ?
(smaller caps, 50-200nF are also exists).
Alex.
I willl design for smd as Thor is ok to stay verroboard and pdip for his own because his stock of parts and/or personal choices about ICs construction
Of course I will ask if I have time to finish it for the BOM with both advices of you. I think Brijac should go faster though, I have some serious health problems to manage into my family. I have verry less time since 15 days, but look time to time in the day pr nigth.
Absolutely, for a pure active loading.
The defined but not very low gain stage impedance inspired me to the CLC; I detail it here: first, pure R, 68R. The Zin of the tube I used plus it's cathode R are in the vicinity of some 180R (it not have so much gm).
Then I simulated a third order passive filter based on these in and out R of filter, resulting in a 20nF of input C (in parallel with the 68R), then a 1.2mH inductor, then a 15nF final cap. A "pi filter".
The tube Zin is not soo low but helps to define a value for the filter. Is anyway far better than trying to filter it using a eg. line output impedance, like 10k or so. In any case, one can use some 180R for the loading of the filter, and uses it with a normal grid input stage.
People wanting more ultrasonic response can alter the filter parts.
I are under impression, with my listenings, that not seemed to degrade the sound, perhaps even the opposite 🙂 the absence of strong staircase steps in the out makes a easier life for lesser amps... and permits less oversampling if the hardware not permits the highest.
Some people wax lyrical about eg. phono pre using LCR RIAA filter, so why not ;-)
+1 😎
That is why the -10V needed
for options to employ theese kind of tubes,
vith -Ug of about -6 to -8V for good operaton point, and slight more mVp-p @ Riv
because the amplification factor is not huge of still availabele but very good 5687, 6N6P and others...
.
And with direct negative grid bias, avoiding 3 passive elements, Ccoupling, Rcathode and Ccathode.
They are critical for BW and PHASE, especially Ccathode and Ccoupling...
🙂
This is the whole idea what for i designed "negative" branch NPN Active IV stage.
.
And You can use the -10V point to Vref for internal cascoding of BJT module. Like You did.
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Still it is an option for cascoding more than 2 modules vith more negative PSm to acheive more negative grid bias and to employ some DHT triode 🙂
.
I will send the schematic. From the vital importance is that almost all of these "negative" NPN oriented circuits has very low THD, with lower values of Riv, for 100-200mV of p-p voltage @ Riv
For furthure amplification and PHASE correction with tube amplification stage...
.
This circuit is OK, BUT why complicate and iduct again automatic grid bias when we have pure negative grid bias?
And unnecessary in existing context, coupling Cin (from negative DC to zero, and then again grom zero to automatic -Ug
with Rcathode...
.
Maybe it was not transparent enough.
I think that this way is more simple, efficient and low thd.
And employs -10V of dac supply unit.
.
Negative grid bias can be slightly adjusted by varying the Io trough the IV and Riv.
Also more important that phase is 0deg, and with one tube (parallel sections) output resistance is about 1K.
.
5697 is set to high voltage, in linear region, with moderate current and not exceeding maximum values. Rload-s of 2x10K should be 10W rated for beating the heat inside the box.
.
Other tubes also are welcome to employ with adjusted settings.
there are 5687 anode curves and model parameters that I made, pretty close match. Also matched with 5687 wersion curves...
.
.
2 Pspice models: one Raytheon other CFP. Very similar You can use each one...
.
Code:
**********************************************
* Created on 04/21/2024 11:12 using paint_kit.jar 3.1
* www.dmitrynizh.com/tubeparams_image.htm
* Plate Curves image file: 5687WA and 5687 Raytheon
* Data source link: Raytheon PDF datas
*----------------------------------------------------------------------------------
.SUBCKT 5687WA_RAY_tools 1 2 3 ; Plate Grid Cathode
+ PARAMS: CCG=4.7P CGP=4.7P CCP=1.3P RGI=2000
* 0.7P added for socket capacitnaces
+ MU=18 KG1=570 KP=142 KVB=300 VCT=0.45 EX=1.414
* Vp_MAX=400 Ip_MAX=70 Vg_step=2 Vg_start=0 Vg_count=14
* Rp=100000 Vg_ac=2.55 P_max=3.75 Vg_qui=-4 Vp_qui=124
* X_MIN=46 Y_MIN=23 X_SIZE=838 Y_SIZE=588 FSZ_X=1686 FSZ_Y=739 XYGrid=true
* showLoadLine=y showIp=y isDHT=n isPP=n isAsymPP=n showDissipLimit=y
* showIg1=n gridLevel2=n isInputSnapped=n
* XYProjections=y harmonicPlot=y dissipPlot=y
*----------------------------------------------------------------------------------
E1 7 0 VALUE={V(1,3)/KP*LOG(1+EXP(KP*(1/MU+(VCT+V(2,3))/SQRT(KVB+V(1,3)*V(1,3)))))}
RE1 7 0 1G ; TO AVOID FLOATING NODES
G1 1 3 VALUE={(PWR(V(7),EX)+PWRS(V(7),EX))/KG1}
RCP 1 3 1G ; TO AVOID FLOATING NODES
C1 2 3 {CCG} ; CATHODE-GRID
C2 2 1 {CGP} ; GRID=PLATE
C3 1 3 {CCP} ; CATHODE-PLATE
D3 5 3 DX ; POSITIVE GRID CURRENT
R1 2 5 {RGI} ; POSITIVE GRID CURRENT
.MODEL DX D(IS=1N RS=1 CJO=10PF TT=1N)
.ENDS 5687WA_RAY_tools
*$
**********************************************
* Created on 04/21/2024 10:53 using paint_kit.jar 3.1
* www.dmitrynizh.com/tubeparams_image.htm
* Plate Curves image file: /Users/zoran/Desktop/Model_Paint_Tools/Graph/
* Data source link:
*----------------------------------------------------------------------------------
.SUBCKT 5687_CSF_tools 1 2 3 ; Plate Grid Cathode
+ PARAMS: CCG=4.7P CGP=4.7P CCP=1.3P RGI=2000
* 0.7P added for socket capacitnaces
+ MU=18.36 KG1=555 KP=128 KVB=300 VCT=0.7 EX=1.4
* Vp_MAX=400 Ip_MAX=70 Vg_step=2 Vg_start=0 Vg_count=14
* Rp=12000 Vg_ac=3.05 P_max=3.75 Vg_qui=-6 Vp_qui=160
* X_MIN=56 Y_MIN=35 X_SIZE=996 Y_SIZE=691 FSZ_X=1830 FSZ_Y=838 XYGrid=true
* showLoadLine=y showIp=y isDHT=n isPP=n isAsymPP=n showDissipLimit=y
* showIg1=n gridLevel2=n isInputSnapped=n
* XYProjections=y harmonicPlot=y dissipPlot=y
*----------------------------------------------------------------------------------
E1 7 0 VALUE={V(1,3)/KP*LOG(1+EXP(KP*(1/MU+(VCT+V(2,3))/SQRT(KVB+V(1,3)*V(1,3)))))}
RE1 7 0 1G ; TO AVOID FLOATING NODES
G1 1 3 VALUE={(PWR(V(7),EX)+PWRS(V(7),EX))/KG1}
RCP 1 3 1G ; TO AVOID FLOATING NODES
C1 2 3 {CCG} ; CATHODE-GRID
C2 2 1 {CGP} ; GRID=PLATE
C3 1 3 {CCP} ; CATHODE-PLATE
D3 5 3 DX ; POSITIVE GRID CURRENT
R1 2 5 {RGI} ; POSITIVE GRID CURRENT
.MODEL DX D(IS=1N RS=1 CJO=10PF TT=1N)
.ENDS 5687_CSF_tools
*$And there is cascoding for "outside" more negative Power supply, and more negative grid bias for other types of tubes. In this example 2A3 is used because of low Ri and low Zout.
-15V of DAC power supply used for reference voltage for added identical cascode module.
-30V (or another -15V but cascoded to existing PS is additional outside power line.
.
THD is very very low...
PSRR is also very low in tube part.
Phase is 0deg...
.
The system showing pretty much the same results with other CFP NPN topologies of this concept.
The main goal when i was interested in this is to use some DHT tube for additional amplification after active BJT circuit, and to be open to adjust for manu different tubes.
.
.
-15V of DAC power supply used for reference voltage for added identical cascode module.
-30V (or another -15V but cascoded to existing PS is additional outside power line.
.
THD is very very low...
PSRR is also very low in tube part.
Phase is 0deg...
.
The system showing pretty much the same results with other CFP NPN topologies of this concept.
The main goal when i was interested in this is to use some DHT tube for additional amplification after active BJT circuit, and to be open to adjust for manu different tubes.
.
.