Building the ultimate NOS DAC using TDA1541A

Not to mention that you will face the issues from paralleling two TDA's output ( their gain is not equal ) , if you look backward on the thread you will find the solution of menber Koldby at post 7279 , otherwise you will face great amount of distortion

I used this trick in my last build ( with an 10 ohm trimer ) and it worked well

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There isn't much in that post. I'm not an expert in the chip but I think the biasing schematics does matter. You bias to +5V pin, this is the return pin for the output signal. This creates some feedback. In John's scheme with +15V, the biasing is independent of the chip. This may or may not matter. Do you have any idea why in your case there was an increased distortion? I'm obviously trying to avoid more complication than needed.

I imagine the resistors at the output play a big role, I plan a mix of Z-foils, RN60D and Mills 5W. What multipot do you use?
 
Not to mention that you will face the issues from paralleling two TDA's output ( their gain is not equal ) , if you look backward on the thread you will find the solution of menber Koldby at post 7279 , otherwise you will face great amount of distortion

I used this trick in my last build ( with an 10 ohm trimer ) and it worked well

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Thanks for the link. He uses balanced not parallel from what I can understand so each output needs a path to the ground. I prefer not to have a pot in the signal path like he has. From a broader perspective, it might as well be that the paralleling is not worth the effort at all.
 
There isn't much in that post. I'm not an expert in the chip but I think the biasing schematics does matter. You bias to +5V pin, this is the return pin for the output signal. This creates some feedback. In John's scheme with +15V, the biasing is independent of the chip. This may or may not matter. Do you have any idea why in your case there was an increased distortion? I'm obviously trying to avoid more complication than needed.

I imagine the resistors at the output play a big role, I plan a mix of Z-foils, RN60D and Mills 5W. What multipot do you use?

I do not have an increased distortion , because I have biaising circuit for every output , and I do not have any feedback too

what is important here is to have the cleanest 5 v ( and all other voltages ) as possible , this why I use LIPO battery supply

I use bourns 3009 multiturn pot

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Forgot to say that balanced , parallel or signed magnitude ( the Koldby build ) are in the same situation regarding the gain differences between the output , so you will have the same issues , each of them with differents solution

fact is that very few people do precise measurements , so they don't know they have a distortion "problem" , many do not ear differences between 0.005 % and 0.05 % of distortion , but there is :cool:

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I disagree with what you are saying, sorry. I also suspect you were constantly confusing the topology: talking about balanced connection (which I understand you tried), while I'm planning a parallel one. In balanced, as I understand each output needs a path to ground (or actually to +5V). This was brought up in the thread somewhere, prob. by Koldby who had problems if there was no path. Also the gain matching matters a lot for obvious reasons. In the parallel connection, where each chip processes both L+R and the outputs are tied together, there is already the path to GND for each output and gain mismatches have no serious impact. Bourns 3009 is a common cermet type. I wouldn't put it near my signal.
 
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In the parallel topology, what is the optimal way to use the I2S attenuators? I plan to use the MVLabs circuits (below), which I assumed individually for each chip (so 6 attenuators in total). The driving chip (CS8414) will see them in parallel on each of the 3 I2S lines. Is that a right use, anybody knows?
1715775068954.png
 
In the parallel topology, what is the optimal way to use the I2S attenuators? I plan to use the MVLabs circuits (below), which I assumed individually for each chip (so 6 attenuators in total). The driving chip (CS8414) will see them in parallel on each of the 3 I2S lines. Is that a right use, anybody knows? View attachment 1310416
One thing that comes to my mind is to decrease the input C by half and increase the input R by 2x in order to keep the RC constant seen by the driving chip the same for parallel connected 1541A.
 
Does anybody have a scope picture of a ‘broken DEM’? I’m getting severe distortion on the output

suspects:
DEM (running at about 666khz), but the trace looks fine as far as I can recall what a normal DEM trace should look like. Also looks like the trace posted above.

Or too much attenuated BCK signal, but I don’t really understand why this would lead to sound but heavily distorted (would expect no sound at all). Attached image is pin 2…

IMG_9376.jpeg
 

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