Hi,
No, I used what was on the amp as main PS caps > BHC 10000uF big cans(AL41 if I remember correctly).
Earlier, I made a low power class A Mosfet amp called ZCA (zero component amp) and there I used one TSHA as C2. But I did not make ABA (with and without charge transfer) comparison to comment. It sounds great to me, powering the front and back horn loaded full/range that I use on my room.
From another comparisons, it seems to me that BHC caps have a dark, weighty bass that is welcome on UCD amps. It cost more than twice the price of the TSHA, though.
Cheers,
M
No, I used what was on the amp as main PS caps > BHC 10000uF big cans(AL41 if I remember correctly).
Earlier, I made a low power class A Mosfet amp called ZCA (zero component amp) and there I used one TSHA as C2. But I did not make ABA (with and without charge transfer) comparison to comment. It sounds great to me, powering the front and back horn loaded full/range that I use on my room.
An externally hosted image should be here but it was not working when we last tested it.
From another comparisons, it seems to me that BHC caps have a dark, weighty bass that is welcome on UCD amps. It cost more than twice the price of the TSHA, though.
Cheers,
M
Hi Eddy,
I went to the safe side and doubled total capacitance, as some (most) of the time C2 will be on their own...
I guess it would be easier for you to let your present caps as C2 and add a 10000uF cap for each rail, as C1...
(easier to wire)
I recall> P channel is IRF5210 and N channel is IRF630...
Good luck,
M
I went to the safe side and doubled total capacitance, as some (most) of the time C2 will be on their own...
I guess it would be easier for you to let your present caps as C2 and add a 10000uF cap for each rail, as C1...
(easier to wire)I recall> P channel is IRF5210 and N channel is IRF630...
Good luck,
M
Hi jims
This applies to all receivers feeding TDA154x.
The idea is minimizing ground-bounce. Ground-bounce increases with both voltage and frequency. Ground-bounce causes (local) voltage drops during current surges, these occur during signal transients. From this point of view, best (DAC) performance can be had running at lowest possible voltage and at lowest possible frequency.
The TDA154x chips have the big advantage of having current steering inputs that will already function reliably using 400mVpp I2S signal levels. This is a significant reduction compared to 5V TTL level signals.
By reducing ground-bounce, both (on-chip) timing jitter and noise are reduced. This is required for best performance.
CS841x receiver sensitivity is specified at 200mVpp, so similar to the TDA154x chips, these receivers can be fed with a 400mVpp SPDIF signal. It's very important to use attenuators on the SPDIF receiver input when using a Toslink receiver, outputting TTL signal levels.
The 150 Ohm resistors will limit surge current a bit, but signal amplitude remains almost unchanged. There is also the problem with impedance matching, TDA154x bit clock is best injected using a low impedance (50 ... 100 Ohms).
This applies to all receivers feeding TDA154x.
The idea is minimizing ground-bounce. Ground-bounce increases with both voltage and frequency. Ground-bounce causes (local) voltage drops during current surges, these occur during signal transients. From this point of view, best (DAC) performance can be had running at lowest possible voltage and at lowest possible frequency.
The TDA154x chips have the big advantage of having current steering inputs that will already function reliably using 400mVpp I2S signal levels. This is a significant reduction compared to 5V TTL level signals.
By reducing ground-bounce, both (on-chip) timing jitter and noise are reduced. This is required for best performance.
CS841x receiver sensitivity is specified at 200mVpp, so similar to the TDA154x chips, these receivers can be fed with a 400mVpp SPDIF signal. It's very important to use attenuators on the SPDIF receiver input when using a Toslink receiver, outputting TTL signal levels.
The 150 Ohm resistors will limit surge current a bit, but signal amplitude remains almost unchanged. There is also the problem with impedance matching, TDA154x bit clock is best injected using a low impedance (50 ... 100 Ohms).
Thanks EC
Great information, your knowledge is amazing. So how do you attenuate the Vpp signal from the CS841X to the TDA154X, while keeping the impedance at 50-100 ohm? The AYAII does not use asynchronous reclocking. The DAC is fed directly from the CS8414 with just 150R in series, as I said in my previous email.
I will measure the input signal to the CS8414. I am curious to see what is the amplitude of the signal being fed to the CS8414. Also on my Monica II. I can't wait to try your dual receiver reclocking circuit. I also order all the parts to make the trans-impedance output stage. Since I do not have a 1543 DAC, yet, I would like to try it first on my monica II (TDA1545). Any recommendations on where to start?
Thanks again
JimS
Great information, your knowledge is amazing. So how do you attenuate the Vpp signal from the CS841X to the TDA154X, while keeping the impedance at 50-100 ohm? The AYAII does not use asynchronous reclocking. The DAC is fed directly from the CS8414 with just 150R in series, as I said in my previous email.
I will measure the input signal to the CS8414. I am curious to see what is the amplitude of the signal being fed to the CS8414. Also on my Monica II. I can't wait to try your dual receiver reclocking circuit. I also order all the parts to make the trans-impedance output stage. Since I do not have a 1543 DAC, yet, I would like to try it first on my monica II (TDA1545). Any recommendations on where to start?
Thanks again
JimS
DEM Reclocking
Hi John,
as per your previous suggestions, I have used my spare 74HC4040 ripple counter to create a 352khz clock signal for DEM reclocking of the TDA1541 DAC. The main Tent XO clock was fed to the HC4040 via a 47ohm resistor. I used my DMM meter to check the pin outs on the HC4040 chip, and identified that PIN 3 was the one I wanted - this was routed via a 47ohm resistor to a spare input on one of the 74HC074s on my reclocker board to create an inverted clock for pin 17.
I am now feeding a + and - 352khz signal on pins 16&17 via 2.2k series resistors, a 430ohm bridge and 100n ceramic caps, and perceive that there is a definate improvement.
I am wondering if there is any benefit in using one of the 1:1 digital pulse transformers that I have spare to create a true differential input of the 352khz signal on pins 16&17?
Brad
Hi John,
as per your previous suggestions, I have used my spare 74HC4040 ripple counter to create a 352khz clock signal for DEM reclocking of the TDA1541 DAC. The main Tent XO clock was fed to the HC4040 via a 47ohm resistor. I used my DMM meter to check the pin outs on the HC4040 chip, and identified that PIN 3 was the one I wanted - this was routed via a 47ohm resistor to a spare input on one of the 74HC074s on my reclocker board to create an inverted clock for pin 17.
I am now feeding a + and - 352khz signal on pins 16&17 via 2.2k series resistors, a 430ohm bridge and 100n ceramic caps, and perceive that there is a definate improvement.
I am wondering if there is any benefit in using one of the 1:1 digital pulse transformers that I have spare to create a true differential input of the 352khz signal on pins 16&17?
Brad
SYNC RECLOCK OF SQUEEZEBOX2
Hi John,
On another note, I am using the sync reclocker circuit as proposed by John Swenson, with my squeezebox2 with good results. In order to provide the 3.3v clock feed to the SB2 John uses a 74HC04 chip and passes the signal through 2 gates to get the correct inversion, however there is also a HCU04 chip in the SB2 that the clock goes through before it gets fed into the XILINX chip, and I am by-passing the Hex inverter in the SB2. does it really matter if i feed an + or inverted clock into the SB2? as I am reclocking anyway?
Brad
Hi John,
On another note, I am using the sync reclocker circuit as proposed by John Swenson, with my squeezebox2 with good results. In order to provide the 3.3v clock feed to the SB2 John uses a 74HC04 chip and passes the signal through 2 gates to get the correct inversion, however there is also a HCU04 chip in the SB2 that the clock goes through before it gets fed into the XILINX chip, and I am by-passing the Hex inverter in the SB2. does it really matter if i feed an + or inverted clock into the SB2? as I am reclocking anyway?
Brad
Hi jims,
First you need to create a 1.2V bias voltage for keeping the TDA154x input at approx. 1.2V DC level (3K3 to Vcc, 1K to GND).
Next the TTL signal is fed to the input using a 3K3 series resistor. This series resistor, and the two resistors used for the DC bias circuit form an attenuator. This attenuator can be used for both WS and DATA signals.
At the moment I only use low impedance for the bit clock (BCK) since this is the most critical signal for timing (jitter). This can be achieved by lowering the resistance values to 100 Ohm and 330 Ohm.
Other method is using a suitable ferrite toroidal core, and construct a 15:1 pulse transformer. I used 15 turns for the primary winding and one turn for the secondary. I used silver-plated wire with thick PTFE insulation in order to maximize the distance of the wire to the ferrite core, this will reduce coupling capacitance between both primary and secondary windings.
Primary inductance is around 470uH, the primary winding is connected to GND (close to the clock source) and to the clock signal using a capacitor, 2n2 will do. The secondary is loaded with 47 Ohms and is connected to the 330 / 100 Ohm bias circuit, the other side goes to the TDA154x bit clock input.
This method prevents bit clock currents running through GND, avoiding picking-up interference. The transformer attenuates unwanted high frequencies, provides required voltage attenuation, while preserving clock signal power (resistive attenuator will dissipate power). The transformer also provides galvanic insulation, reducing back-interference from connected load to the clock source.
The D1M has such a pulse-transformer based attenuator for BCK. Output amplitude equals approx. 334mVpp.
You could start by using very clean power supplies, and that's far more difficult than expected. I am aiming at approx. 30nV root Hz and approx. 0.02 Ohm impedance, this excludes many conventional power supplies, often used in digital audio equipment.
78xx regulator produces over 42,000nv root Hz noise, basically useless for these kind of demanding applications. There are some ultra-low noise / low drop-out regulators (Micrel) that manage to achieve around 270nV root Hz. I used these in the SPDIF receiver modules.
But there are other problems besides noise, there is mains hum and interference, ground loops, decoupling capacitor-pair oscillations, and crosstalk between basically everything connected to the power supply.
I started by using the new Floating CT power supply, this interrupts both GND and power supply connections, creating a true "floating" power supply, reducing the effect of ground loops.
In order to reduce ripple voltage, the floating CT supply is followed by a capacitance multiplier, emulating approx. 750,000uF.
The low-ripple voltage is then stabilized (9V4) by using a discrete series regulator that provides low noise.
Next, each sub-circuit is powered by a separate hybrid power supply that connects to the main 9V4 power supply.
The hybrid regulators consist of a capacitance multiplier emulating 40,000,000uF (using a very high-gain triple-darlington). The capacitance multiplier feeds a precision constant current source (also built around a triple-darlington), that uses a highly accurate, filtered 2.048V bandgap voltage reference. The constant current source provides high series impedance. The constant current source feeds the actual shunt voltage regulator through a passive LC filter. The shunt regulator is based on 8 x TS431 (48nV root Hz) in parallel. Since output voltage is higher than the TS431 internal 2V5 reference voltage, noise levels are amplified. But the paralleling of devices reduces these noise levels again. In practice, noise levels of below approx. 30nV root Hz could be achieved. This voltage passes another passive LC filter that reduces noise to even lower levels, and maintains performance at higher frequencies.
The hybrid regulators require approx. 30 seconds to "power-up", and the CS8416 receivers now require a voltage monitor chip that produces a reliable reset signal (the slow power-supply rise prevents using simple RC reset circuits for the CS8416).
I plan to put these hybrid regulators on a small 1 x 2cm PCB, using SMD parts. The D1M prototype now runs on 5 of these hybrid regulators.
First you need to create a 1.2V bias voltage for keeping the TDA154x input at approx. 1.2V DC level (3K3 to Vcc, 1K to GND).
Next the TTL signal is fed to the input using a 3K3 series resistor. This series resistor, and the two resistors used for the DC bias circuit form an attenuator. This attenuator can be used for both WS and DATA signals.
At the moment I only use low impedance for the bit clock (BCK) since this is the most critical signal for timing (jitter). This can be achieved by lowering the resistance values to 100 Ohm and 330 Ohm.
Other method is using a suitable ferrite toroidal core, and construct a 15:1 pulse transformer. I used 15 turns for the primary winding and one turn for the secondary. I used silver-plated wire with thick PTFE insulation in order to maximize the distance of the wire to the ferrite core, this will reduce coupling capacitance between both primary and secondary windings.
Primary inductance is around 470uH, the primary winding is connected to GND (close to the clock source) and to the clock signal using a capacitor, 2n2 will do. The secondary is loaded with 47 Ohms and is connected to the 330 / 100 Ohm bias circuit, the other side goes to the TDA154x bit clock input.
This method prevents bit clock currents running through GND, avoiding picking-up interference. The transformer attenuates unwanted high frequencies, provides required voltage attenuation, while preserving clock signal power (resistive attenuator will dissipate power). The transformer also provides galvanic insulation, reducing back-interference from connected load to the clock source.
The D1M has such a pulse-transformer based attenuator for BCK. Output amplitude equals approx. 334mVpp.
You could start by using very clean power supplies, and that's far more difficult than expected. I am aiming at approx. 30nV root Hz and approx. 0.02 Ohm impedance, this excludes many conventional power supplies, often used in digital audio equipment.
78xx regulator produces over 42,000nv root Hz noise, basically useless for these kind of demanding applications. There are some ultra-low noise / low drop-out regulators (Micrel) that manage to achieve around 270nV root Hz. I used these in the SPDIF receiver modules.
But there are other problems besides noise, there is mains hum and interference, ground loops, decoupling capacitor-pair oscillations, and crosstalk between basically everything connected to the power supply.
I started by using the new Floating CT power supply, this interrupts both GND and power supply connections, creating a true "floating" power supply, reducing the effect of ground loops.
In order to reduce ripple voltage, the floating CT supply is followed by a capacitance multiplier, emulating approx. 750,000uF.
The low-ripple voltage is then stabilized (9V4) by using a discrete series regulator that provides low noise.
Next, each sub-circuit is powered by a separate hybrid power supply that connects to the main 9V4 power supply.
The hybrid regulators consist of a capacitance multiplier emulating 40,000,000uF (using a very high-gain triple-darlington). The capacitance multiplier feeds a precision constant current source (also built around a triple-darlington), that uses a highly accurate, filtered 2.048V bandgap voltage reference. The constant current source provides high series impedance. The constant current source feeds the actual shunt voltage regulator through a passive LC filter. The shunt regulator is based on 8 x TS431 (48nV root Hz) in parallel. Since output voltage is higher than the TS431 internal 2V5 reference voltage, noise levels are amplified. But the paralleling of devices reduces these noise levels again. In practice, noise levels of below approx. 30nV root Hz could be achieved. This voltage passes another passive LC filter that reduces noise to even lower levels, and maintains performance at higher frequencies.
The hybrid regulators require approx. 30 seconds to "power-up", and the CS8416 receivers now require a voltage monitor chip that produces a reliable reset signal (the slow power-supply rise prevents using simple RC reset circuits for the CS8416).
I plan to put these hybrid regulators on a small 1 x 2cm PCB, using SMD parts. The D1M prototype now runs on 5 of these hybrid regulators.
Thanks EC
I will try out your suggestions this weekend. My box from Mouser arrived, so I should have all of the fets to try your output buffer and the CT-capacitance multiplier PS. For the 15:1. I have some 30 AWG Kynar insulated wire and some fairly small toroidal cores. Would these work? I also have some solid silver wire and spagetti teflon tubing. Which if either would you recommend.
JimS
I will try out your suggestions this weekend. My box from Mouser arrived, so I should have all of the fets to try your output buffer and the CT-capacitance multiplier PS. For the 15:1. I have some 30 AWG Kynar insulated wire and some fairly small toroidal cores. Would these work? I also have some solid silver wire and spagetti teflon tubing. Which if either would you recommend.
JimS
Walt Jung's tests on 7915 regs for the "Super Reg" articles showed two examples had 4,600nV root Hz and 2,600nV root Hz at 1khz respectively, whereas a 7815 tested at 350nV root Hz at 1khz.
What are you basing the 42,000nV/root Hz for a 78xx on?
Walt Jungs tests can be found on page 24 of this article:
http://waltjung.org/PDFs/Regs_for_High_Perf_Audio_2_A.pdf
Hi spzzzzkt,
LM7805 datasheet specs: 42uV root Hz typical, this equals 42,000nV root Hz.
Fairchild 7805 , datasheet page 3, 42uV
KEC 7805, datasheet page page 3, 50uV
TI 7805, datasheet page 4, 40uV
Hitachi, datasheet page 4, 120uV
Panasonic, datasheet page 2, 40uV
ST, datasheet page 5, 40uV
Noise levels can vary between 78xx regulators of different manufacturers, but most datasheets indicate approx. 40uV root Hz @ 5V.
I verified these noise levels using an ultra low noise 1000x pre-amp / probe. And I have to conclude that datasheet specs are quite accurate.
78xx noise levels can be reduced by connecting a large capacitance (220 ... 1000uF) on the regulator output.
NSC LM7815 datasheet page 3 specifies 90uV or 90,000nV noise. 350nV is around 257 times lower than specified, so I have some doubts if this value is correct, but you never know.
LM7805 datasheet specs: 42uV root Hz typical, this equals 42,000nV root Hz.
Fairchild 7805 , datasheet page 3, 42uV
KEC 7805, datasheet page page 3, 50uV
TI 7805, datasheet page 4, 40uV
Hitachi, datasheet page 4, 120uV
Panasonic, datasheet page 2, 40uV
ST, datasheet page 5, 40uV
Noise levels can vary between 78xx regulators of different manufacturers, but most datasheets indicate approx. 40uV root Hz @ 5V.
I verified these noise levels using an ultra low noise 1000x pre-amp / probe. And I have to conclude that datasheet specs are quite accurate.
78xx noise levels can be reduced by connecting a large capacitance (220 ... 1000uF) on the regulator output.
NSC LM7815 datasheet page 3 specifies 90uV or 90,000nV noise. 350nV is around 257 times lower than specified, so I have some doubts if this value is correct, but you never know.
Sorry If I'm being dense - aren't the data sheet noise given over a defined bandwidth?
The ST7805 datasheet uses 10hz-100khz for example. nv/root hz is noise density for 1 hz and from what I understand to apply a nV/root Hz figure you would multiply the square root of the bandwidth by nV/root Hz to get a rms noise figure for the specified bandwidth.
If you work backwards and divide the datasheet 50 uV noise figure by the square root of the bandwidth you get a noise density of 168nV/root Hz in the case of the ST7805. Applying the same method to the NSC LM7815/LM340 you'd get 285 nV/root Hz. This seems more in line with Walt Jung's findings.
edit: (changed example to reflect one of John's above)
The ST7805 datasheet uses 10hz-100khz for example. nv/root hz is noise density for 1 hz and from what I understand to apply a nV/root Hz figure you would multiply the square root of the bandwidth by nV/root Hz to get a rms noise figure for the specified bandwidth.
If you work backwards and divide the datasheet 50 uV noise figure by the square root of the bandwidth you get a noise density of 168nV/root Hz in the case of the ST7805. Applying the same method to the NSC LM7815/LM340 you'd get 285 nV/root Hz. This seems more in line with Walt Jung's findings.
edit: (changed example to reflect one of John's above)
I guess most of you read this article
Regarding PLL in the USB chip.
http://www.6moons.com/audioreviews/wavelength2/brick_2.html
Regarding PLL in the USB chip.
http://www.6moons.com/audioreviews/wavelength2/brick_2.html
Hi ECDesigns
I have been puzzled by the transimpedance I/V circuits for the past few days.
I manage to obtain the DC operating voltage as you mention in the following diagram.
Kindly check if the R2, R3 value is correct or need to be replaced. C2 is 4u7.
The problem is the DC voltage at C2 input is 8.1V DC and the output is droping from 8.9V to about 300mV, and it takes about 4 minutes to drop to 300mV. With that output DC so high, I cant connect it to my amp.
I have been puzzled by the transimpedance I/V circuits for the past few days.
I manage to obtain the DC operating voltage as you mention in the following diagram.
Kindly check if the R2, R3 value is correct or need to be replaced. C2 is 4u7.
The problem is the DC voltage at C2 input is 8.1V DC and the output is droping from 8.9V to about 300mV, and it takes about 4 minutes to drop to 300mV. With that output DC so high, I cant connect it to my amp.