Bode plot reveals instability - solution advice sought

Jump to Latest
#61
It's "Add plot" (not add trace), but it works like a charm:
1738176214524.png
 
#63
That looks about right and gives you a phase margin of about 73 degrees, which is quite typical. If you post the QSPICE files I can double check for you.

But if you did everything correctly, that amplifier shouldn't oscillate during normal circumstances. You can "torture" it by replacing the resistive dummy load with capacitors, inductors and combinations thereof.
 
  • Thank You
Reactions: Terry2000
#65
njswede said:
If you post the QSPICE files I can double check for you.
Click to expand...
KSA-1015-994_Bode-04-02.PNG

Thanks for your offer to check my work to date, QSPICE file attached. The Vbe bias is a simple affair...
Phase margin is better than 80 degrees; square waves need to be magnified to reveal a nasty on the corner which I hope is benign.

Cheers
 

Attachments

#66
I have attempted a better topology to get a flatter response without the slight drop before rising like my previous attempt. I would like to ask if someone could eyeball the Bode plot to check it. I'm surprised to see the phase margin 133 degrees but it does get rid of the drop seen in my previous plot.
Also, have I understood B Cordell information regarding R9/R12 to be reading 26mV each?

Cheers


Bode_EF2.PNG
 

Attachments

  • Schem_EF2.PNG
    Schem_EF2.PNG
    69.2 KB · Views: 44
#67
I don't trust your simulation at high frequencies because of where you are breaking the loop. If you move your AC source between your output and the feedback network then I would believe your results. You have to have a large impedance mismatch on both sides of the AC source for all frequencies of interest when you break the loop this way. Looking into the base of a PNP is not a high impedance at some frequency.
Also, it seems dangerous to have the loop gain stop at a gain of one even if you have a large phase margin. Some one with more experience could over rule me on that opinion. I would want a design with some gain margin and some phase margin.
 
#68
James361 said:
I would want a design with some gain margin and some phase margin.
Click to expand...
Thanks for your input. The design is D Self's blameless amp schematic from his book. With the small signal transistors I selected this is the result; Self doesn't specify the parts he used. I'll try the Bode plot capture again using your suggestion.
What figure/number constitutes 'some gain margin and some phase margin'?

Cheers
 
#69
I am no authority but I would think that a -20 db gain margin and a 30 degree phase margin would be a very stable design. Of course any gain and phase margin is good on paper but you are trying to build in some margin for model variation and layout sensitivity so the circuit will be stable. I am not sure that your circuit is stable because the loop gain of one and the phase of zero are very close together at about 20 MegaHertz.
 
#73
Update:
I discovered that by reducing the de-generation resistor value for the top of LTP from R100 to R22 corrected phase margin to 86 degrees from 133!

I don't like the hump to the right. Would this be obviously audible or can I ignore this?

Cheers
 

Attachments

  • Bode-17-02.PNG
    Bode-17-02.PNG
    71.8 KB · Views: 28
Last edited:
You must log in or register to reply here.
Top Bottom