I was really trying to get something build, get a well studied low distortion design, get the pcb and worry about it the simulation to nail down the value of the components while the pcb is being fab. I guess this is more involve than a quick read and build.Like a kid with a new "toy" ... huh ?
LT = a schematic/service manual that "works".
OS
The thing that surprised me is the effect of the base current. All it take is slight imbalance of the offset due to base current to upset the voltage at point A which directly affect the current through the VAS. The offset due to the base current is half the problem!!!!
I guess I have no choice but to stop and really get into LTspice to simulate distortion of different configuration to choose the best design. That, I have no idea how to do yet.
Get a fully commented and working low distortion LT spice amp simulation ,
reverse engineer (play with) the settings ,values, and comments.
As a file , and changes can be a "save as" deviation (the working original is still
around).
OS
reverse engineer (play with) the settings ,values, and comments.
What is this? Is it different from LTspice IV?
Ha ha, you wrote two sentences and I don't follow neither one of them. Can you explain a little more?
Thanks
Yes , LT 4.
An LT spice file can be made fully "self contained" with the models included
as either a separate text or commented right on the schematic.
Edit - the Cordell / Keentoken BJT models are standard fare on the forum.
With a few other (syn08) advanced entries.
A compete amp that is set to show 20K thd can also show 1K,10K ... 100k.
I include comments for all the tests (THD , PSRR , slew rate/square wave, bode).
You copy/paste those as directives to run different tests.
What I meant by "reverse engineer" is that you can download a file from a
more advanced user and just copy/ paste his directives (full or partial) to
your test simulation.
While experimenting like this , keep the original (working) LT file as backup
and reference.
If you want one like this , I have one (Bob's example LIN amp).
(and just about every other one there is , as well)
OS
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R14/R16 != stop-gap?
Okay, agreed, it's a simple and elegant solution. But it is a solution for a problem, which shouldn't have been created in the first place. Another option, for those who won't sacrifice high open loop gain at low frequencies, is a common mode control loop (CMCL), which cost another six trannies, see: Super TIS fig. 9. Admittedly, it does work, though it's not the way to go: way to too complex. IMHO, this complementary Sloan front-end is a dead-end. The basic concept is just plain wrong.
Cheers, E.
Hi Bob,
Okay, agreed, it's a simple and elegant solution. But it is a solution for a problem, which shouldn't have been created in the first place. Another option, for those who won't sacrifice high open loop gain at low frequencies, is a common mode control loop (CMCL), which cost another six trannies, see: Super TIS fig. 9. Admittedly, it does work, though it's not the way to go: way to too complex. IMHO, this complementary Sloan front-end is a dead-end. The basic concept is just plain wrong.
Cheers, E.
Edmond, one other question if I may: is there a significant penalty associated in reducing the standing currents in the input stage, allowing TO-92 parts to be substituted for the TO-126 devices, and use of SOT-23 devices where TO-92 is currently specified.
If you aren't able to make a PCB layout available, I would like to do one of my own at some stage, and my preference would be to use mostly surface mount parts to achieve very tight routing.
If you aren't able to make a PCB layout available, I would like to do one of my own at some stage, and my preference would be to use mostly surface mount parts to achieve very tight routing.
This is something I have been puzzling over for over a week now. Been trying to layout a simplified version. It's not obvious how best to approach the PCB layout for the SuperTis front end. It would be easy to layout a PCB as per schematic but this would be massively sub-optimal. Trying to keep loop areas small and power rails out of the way always results in a compromise at the end....
Would be interested in other peoples ideas regarding layout for this front end.
Paul
Hi Christian,
I don't think there's a significant penalty when the standing currents are lowered somewhat, halved or so. The reason I've specified the KSC3503 and KSA1381 is simply that I've a lot of them and also that they have a rather high VAF (Early voltage).
Cheers, E.
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Hi Edmond,
I don't think we are far apart on our views, regardless of the semantics.
Here's the thing: Lots of amplifiers are built with this type of full complementary front-end. We can argue the pros and cons of this approach, but it is indeed popular. It is a symmetrical, convenient way to drive a push-pull VAS. But most of the ones that I have seen that work do not use current mirror loads on the input LTPs.
The use of current mirror loads is a well-known good thing, if for no other reason than to keep the LTP collector currents balanced. Most of the full-complementary designs out there use just the old-fashioned resistor load for one side of the IPS, and use that node to drive a 1T or Darlington VAS. This generally gives low gain and poor balance to the IPS. Slone's circuit is well-intentioned in introducing current mirror loads to the full complementary input stage, but it doesn't work.
So, those who still wish to use that topology should be made aware of ways to make it work, and the trade-offs involved. Once again, your circuit is a very good approach, but some may choose a different approach.
Cheers,
Bob
Hi Andrew,
I think you need to start off by simulating exactly the figure in my book, not just half the circuit and not with overly-large current mirror degeneration resistors. Then, with a good working implementation with ideal matched transistors and known nominal VAS standing current, tweak the Vbe offsets and transistor betas a bit and see what happens and report the VAS standing current. Bear in mind that in the full circuit, the bases of the PNP and NPN LTPs are tied together with low impedance, and this makes a difference.
I personally would never go for a PWB until after I have thoroughly simulated the design and usually after having built the design on perf board and measured it. That is the way I build all of my amplifiers. My perf board layouts are neat and compact, and are arranged largely like the PCB layout. 90% of the connections are made by bare component wires component-to-component on the wiring side.
Cheers,
Bob
> but some may choose a different approach.
Hi Bob,
Well, that remains to be seen. Most of the workable solutions boil down to reducing the VAS gain. That's precisely what I also did, though with a little twist: I've reduced the (current) gain a little further, more precisely, to just unity. In this case, the loss of gain has to be compensated elsewhere, of course, but that's essentially a side issue.
Cheers, E.
Hi Bob,
Well, that remains to be seen. Most of the workable solutions boil down to reducing the VAS gain. That's precisely what I also did, though with a little twist: I've reduced the (current) gain a little further, more precisely, to just unity. In this case, the loss of gain has to be compensated elsewhere, of course, but that's essentially a side issue.
Cheers, E.
Hi Mr. Cordell
This is Alan
I did try that at the beginning. Attached is the original file before I simplified to one sided. The result seems to be worst. For one, I originally use 2mA tail current. Lowering the tail current improve the situation, but if I follow the 10:1 degeneration, The gain is going to get low and won't be much better than just using resistor load.
Thanks.
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Hi Bob,
Thank you for taking the time to answer to my previous question regarding folded drivers and reactive loads.
Have another basic question. That probably has an equally simple answer...
My tiny mind is struggling to work why current mirrors are not a good idea for a fully complementary input stage. Why do they not work as expected?
Thank you,
Paul