Bob Cordell said:
However, if you are referring to the dual complementary differential input stage arrangement you use in your 12W amplifier, I do not think it is a very good design, but I have not bothered to simulate it, since it appears to be sub-optimal by inspection.
Well thank you very much for the in-depth analysis. Every design is "sub-optimal" to a degree. The design was only intended to be modest improvement over the standard miller-compensated, symetrical topology to see how good it can be made to perform, and it does perform quite well.
I have, for instance, already commented on the fact that the low impedance presented at the base of each VAS transistor (with the reduced NFB) isn't a serious issue due to the high input impedance of the tripple emitter output stage.
The design has been sinulated by Edmond at 8ppm THD-20 at the rated output power into 4 ohms. I have built it an my measurements confirm <0.001% THD 20Hz to 20kHz.
Is that poor?
For a design that only uses bog standard, electronics hobby-store transistors and doesn't resort to the complexities of error correction, fancy feedback methods or nested feedback loops, I think the performance is rather good.