Bob Cordell Interview: Error Correction

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#2,723
Tim__x said:
Though it's certainly not a phase splitter. I have to agree with Traderbam in that there is nothing new in that circuit. Only the schottky diodes are even remotely unusual.
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Hi Tim,

As I've already told, the Schottky diodes do nothing, forget them (I was just fooled by a simulation). Of course this circuit isn't new, as it comprises of an input stage, a VAS and an output stage, Besides, I've never claimed that it is new. But Brian thought it wasn't new because of a nonexistent phase splitter, which is utterly nonsense.

Cheers, Edmond
 
#2,727
Of course this circuit isn't new, as it comprises of an input stage, a VAS and an output stage, Besides, I've never claimed that it is new. But Brian thought it wasn't new because of a nonexistent phase splitter, which is utterly nonsense.
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No Edmond you didn't claim it was new. It was PB2 who asked whether the circuit was new and I said it wasn't.
BTW I appreciate the appropriate sensitivity shown by Variac in the interests of keeping the peace. But I'm not feeling provoked by your unequivocal disagreement with my description of the circuit. 😎
 
#2,728
Tim__x wrote:
Though it's certainly not a phase splitter. I have to agree with Traderbam in that there is nothing new in that circuit. Only the schottky diodes are even remotely unusual.
Click to expand...
Hi Tim. I was refering to the error signal being phase split into the two collector currents of the two input transistors, Q2 and Q3. These anti-phase error signals then get subtracted and reunited at the bases of Q7 and Q8. Perhaps you have a different definition of a phase splitter in mind?
Brian
 
#2,730
Re: Practical aspects of error correction

Bob Cordell said:
A couple of times people have expressed concern about the need to adjust the pot in the EC circuit (if you have chosen to implement it with a pot).

As amplifiers using EC are usually going to be delivering very low amounts of distortion, the question comes up of how to do such an adjustment without an expecially sensitive THD analyzer.

One approach that I have used is to tap off the signal that enters the error-correcting output stage of the amplifier in closed-loop operation. This is essentially the VAS signal, but wants to be the buffered version of it. A resistive center tap off of the first emitter follower pair in the EC circuit works well.

If you look at this node, it essentially contains the inverse of the output stage distortion, since the global feedback tends to drive the distortion at the output of the amplifier to zero. With this view of the essentially raw distortion of the output stage (which will typically be well above 0.001%), it is easy to tweak the pot for a minimum of the distortion at 1 kHz, since this is a static balance of the EC stage that you are shooting for.
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Thanks for this tip, Bob - great stuff!
 
#2,731
traderbam said:
No Edmond you didn't claim it was new. It was PB2 who asked whether the circuit was new and I said it wasn't.
....................................
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Okay, you didn't claim it, you only said it. Does this mean to you that this minor subtlety makes the difference whether to explain or not why it wasn't new?


........ I was refering to the error signal being phase split into the two collector currents of the two input transistors, Q2 and Q3. These anti-phase error signals then get subtracted and reunited at the bases of Q7 and Q8. Perhaps you have a different definition of a phase splitter in mind?
Brian
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The currents of the two input transistors are in phase, that should be crystal clear to everyone. Besides, if they were in anti phase the signal at the bases of Q7 and Q8 would be zero.

One more thing, these signals are no error signals, just signals (unless, of course, you consider the signal at the output terminal also as an error signal).
 
#2,732
Edmond,
I infer from your pithy comments that you think I have an obligation to explain things to you. I don't.

The currents of the two input transistors are in phase, that should be crystal clear to everyone. Besides, if they were in anti phase the signal at the bases of Q7 and Q8 would be zero.
Click to expand...
If you were to sketch out an ac small-signal model (V sources are short circuits and I sources are open circuits) I'm confident it would become crystal clear to you that the currents are out of phase. 😉

One more thing, these signals are no error signals, just signals (unless, of course, you consider the signal at the output terminal also as an error signal).
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😀 You are teasing me now.
 
#2,733
Re: Re: Re: Re: Re: Practical aspects of error correction

Bob Cordell said:
No, Edmond. You raised the bar to 1 ppm. You used EC to get there. If your circuit is as good as EC, you need to use it to get to 1ppm.

Cheers,
Bob
Click to expand...

Hi Bob,

Regarding the PGP amp, indeed, we raised the bar to 1ppm, but that is completely beside the point.

Referring to your own comment ( http://www.diyaudio.com/forums/showthread.php?postid=1309536#post1309536 ) there exist three different points of view on HEC. For convenience, I'll repeat them here in short:
1. The error correction view.
2. The negative feedback view.
3. The adaptive low feedback view.
According to you, all three ways of looking at HEC are valid. Perhaps, but that doesn't matter. What really matters is which of these three 'valid' views reveals the true nature of HEC and that is only number 2, while the other views will easily lead to erroneous conclusions, such as a (nonexistent!) 'adaptive' feedback or a far better stability.

Therefore, and only therefore, I've dropped the schematic of an alternative OPS, based on conventional NFB, just to show that under comparable circumstances, for example equal Fc of the frequency compensation, the performance is exactly the same. Actually, the distortion is even slightly lower (THD20=50ppm), because the error produced by the drivers, is also reduced by the NFB.

I've mentioned a slight overshoot. However, If we look at the square wave response of one of your simulations ( http://www.diyaudio.com/forums/showthread.php?postid=1312940#post1312940 ) it appears that also HEC produces some overshoot.

As for building the thing, why should I? You know that my simulation are damn reliable. Besides, I made a direct comparison between the two topologies. Perhaps that the figures, in an absolute sense, are a bit inaccurate, but relative to each other, such inaccuracies don't matter.


Cheers, Edmond.
 
#2,735
traderbam said:
Edmond,
I infer from your pithy comments that you think I have an obligation to explain things to you. I don't.
Click to expand...

Considering your own words:

"You may have noticed that I choose not to give direct design advice in this forum, except for basic design help. I do try to expose myths and subjective claims that cannot be substatiated objectively. Otherwise, I choose to pose questions and make oblique comments that are intended to cause people to think differently about the problem."

I should have known better and not expect a meaningful answer at all.


If you were to sketch out an ac small-signal model (V sources are short circuits and I sources are open circuits) I'm confident it would become crystal clear to you that the currents are out of phase. 😉
Click to expand...

The collector currents of Q2 and Q3 have an opposite sign, that's true. However, as these signals also have an opposite magnitude, the final result is in phase. - x - = +, you know. 🙂


You are teasing me now.
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No, just joking. 😀

Cheers, Edmond.
 
#2,737
Re: Re: Re: Re: Re: Re: Practical aspects of error correction

Edmond Stuart said:


Hi Bob,

Regarding the PGP amp, indeed, we raised the bar to 1ppm, but that is completely beside the point.

Referring to your own comment ( http://www.diyaudio.com/forums/showthread.php?postid=1309536#post1309536 ) there exist three different points of view on HEC. For convenience, I'll repeat them here in short:
1. The error correction view.
2. The negative feedback view.
3. The adaptive low feedback view.
According to you, all three ways of looking at HEC are valid. Perhaps, but that doesn't matter. What really matters is which of these three 'valid' views reveals the true nature of HEC and that is only number 2, while the other views will easily lead to erroneous conclusions, such as a (nonexistent!) 'adaptive' feedback or a far better stability.

Therefore, and only therefore, I've dropped the schematic of an alternative OPS, based on conventional NFB, just to show that under comparable circumstances, for example equal Fc of the frequency compensation, the performance is exactly the same. Actually, the distortion is even slightly lower (THD20=50ppm), because the error produced by the drivers, is also reduced by the NFB.

I've mentioned a slight overshoot. However, If we look at the square wave response of one of your simulations ( http://www.diyaudio.com/forums/showthread.php?postid=1312940#post1312940 ) it appears that also HEC produces some overshoot.

As for building the thing, why should I? You know that my simulation are damn reliable. Besides, I made a direct comparison between the two topologies. Perhaps that the figures, in an absolute sense, are a bit inaccurate, but relative to each other, such inaccuracies don't matter.


Cheers, Edmond.
Click to expand...


Hi Edmond,

First, I stick to my point that multiple views of a technology like EC are valuable and provide insight. Your one-dimensional view of HEC as only negative feedback is valid, and I have never disputed that, but it is not the only valid way to look at it. Your "my way or the highway" approach is less helpful.

I know your simulations are quite good, but as far as I know, you have not shown a simulation of it as a complete amplifier showing good stability and THD below 10 ppm even.

Can you show us an ac frequency/phase response plot of your current preferred version of this output stage out to about 20 MHz? Can you also show us this plot into 4 ohms load?

I'm curious, why did you use different gate stopper resistors for your two output MOSFETs?

Cheers,
Bob
 
#2,738
Error Correction Sensitivity

Awhile back a question arose as to the sensitivity of the effectiveness of error correction to errors in resistor tolerances in the error correction balance network, e.g., the sensitivity of the tweak pot.

I had speculated that the sensitivity was such that a net 1% error would likely limit the improvement by EC to a factor of about 100:1 or 40 dB. Some doubted this and thought that it would be much more sensitive than this; i.e., that a 1% error would cause EC effectiveness to go well below 40 dB.

I checked this out in simulation on a version of my EC circuit with a single pair of Toshiba MOSFETs biased at 150 mA driving an 8 ohm load at 1 kHz at 9V peak (where crossover distortion is near greatest).

Without EC, the THD was 0.15%.

With EC, where in this circuit the resistor where the trim pot would go was 18 ohms at optimum, THD was 0.00032%, for an error correction distortion correction factor of 469 (almost 54 dB).

It should be noted that the total effective resistance in the path where this 18 ohm trim resistor was located was 170 ohms, so a 1% error would correspond to a 1.7 ohm change in the value of the 18 ohm trim resistor.

With a 1% error introduced in either direction, THD rose to 0.00155%, corresponding to an error correction factor of 96.8, or about 40 dB.

With a 5% error introduced in either direction, THD rose to 0.0078%, corresponding to an error correction factor of 19.2, or nearly 26 dB. Of course, in rough terms according to my speculation, a 5% error would limit EC effectiveness to 20:1.

So it looks like my hypothesis was correct.

This means that if you choose to ditch the trim pot and properly center your design with 1% resistors, you'll get an EC effectiveness of about 40 dB unless you get extremely unlucky with the spread of the 1% resistors. 40 dB of improvement from EC without even using a trim pot is pretty darn good, in my opinion.

Cheers,
Bob
 
#2,739
Re: Error Correction Sensitivity

Bob Cordell said:
Awhile back a question arose as to the sensitivity of the effectiveness of error correction to errors in resistor tolerances in the error correction balance network, e.g., the sensitivity of the tweak pot.
Click to expand...

Your simulation results are matching my implementation results. I think it's confirmed now that much better than 1% resistors are needed if the target is to reach 100ppm open loop THD.

Again from a practical perspective, in a new implementation it is pretty difficult to guess what's the optimum resistor value (due to the impact that the rest of the circuit has on the Hawksword balance). You will still need to initially trim the balance, then hopefully you'll find a standard value in the (better than) +/-1% spread from the optimal value. You will of course note that the errors may cumulate here as well.

Originally, I tried to use the values in your schematic with the new trannies. 680ohm/330ohm was way off the balance and I was unable to find a standard value to provide the balance. I had to try several pairs end ended up with 561ohm/250ohm both 0.1%.

Under these circumstances, the open loop THD was anywhere between 70ppm and 120ppm for the four EC OPS stages that I built (with 561ohm/250ohm fixed, no trimming). The large spread is obviously due to other component variations (all other resistors were 1% and trannies were not matched).

So I'm afraid that for a target of under 100ppm open loop THD, better than 1% precision resistors are required, preferably 0.1%. For such a target, the EC OPS sensitivity is pretty high.

As I said before, breaking the 1ppm barier with an EC OPS at over 100ppm open loop is pretty darn difficult. Yes, you need more than 40dB loop gain to bring the overall THD under 1ppm.
 
#2,740
Re: Re: Error Correction Sensitivity

syn08 said:


Your simulation results are matching my implementation results. I think it's confirmed now that much better than 1% resistors are needed if the target is to reach 100ppm open loop THD.

Again from a practical perspective, in a new implementation it is pretty difficult to guess what's the optimum resistor value (due to the impact that the rest of the circuit has on the Hawksword balance). You will still need to initially trim the balance, then hopefully you'll find a standard value in the (better than) +/-1% spread from the optimal value. You will of course note that the errors may cumulate here as well.

Originally, I tried to use the values in your schematic with the new trannies. 680ohm/330ohm was way off the balance and I was unable to find a standard value to provide the balance. I had to try several pairs end ended up with 561ohm/250ohm both 0.1%.

Under these circumstances, the open loop THD was anywhere between 70ppm and 120ppm for the four EC OPS stages that I built (with 561ohm/250ohm fixed, no trimming). The large spread is obviously due to other component variations (all other resistors were 1% and trannies were not matched).

So I'm afraid that for a target of under 100ppm open loop THD, better than 1% precision resistors are required, preferably 0.1%. For such a target, the EC OPS sensitivity is pretty high.

As I said before, breaking the 1ppm barier with an EC OPS at over 100ppm open loop is pretty darn difficult. Yes, you need more than 40dB loop gain to bring the overall THD under 1ppm.
Click to expand...


Ovidiu,

There is something not right here. I don't think the results are matching, maybe off by a factor of ten.

In my post above, the open loop output stage with EC with balance off by 1% was yielding THD of 0.00155 %, which is only 15.5 ppm. This is way under 100 ppm.

Please also understand that the trim location I use is a single resistor in series with the junction of the two emitter resistors of the error pair. The optimum value of this trim resistor is only on the order of 10% of the total effective resistance in the circuit at that point, so a 1% change in balance corresponds to about a 10% change in this trim resistor, so there is no big issue with available resistor value quantization.

Cheers,
Bob
 
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