Bob Cordell Interview: Error Correction

[mikeks]

Hi Andy,

I think this really is a case of what one loses on the swings one gains on the slides. 🙂

R6/R13 need to be kept small to maximise voltage efficiency, and mitigate against anomalous variations in bias due to their voltage drops.

Simultaneously, R24/37 are required to set the diff. stage's voltage gain to two in this case.

Using, say, 511R calls for at least +/-10V(!) to bias the system.

However, you are right in principal; any ideas on an optimal value for the load resistor and EC loop standing current?

 

[mikeks]

Hi Andy,

I've used 511R for load and half that in the diff. pairs to generate a gain of two with current reduced to 10mA.

Bias has to go up to over 14V, but a 1 ohm load can now be driven to +/-40V without the diff amps saturating, at least in SPICE.

It'll have to wait until the weekend for component swaps in the real thing.

Thanks for that observation.

See attached for unity gain diff amps, and gain of two diff amps preceded by attenuation.

Any further useful adjustments will be appreciated.

Cheers.

 

[andy_c]

I think this really is a case of what one loses on the swings one gains on the slides. 🙂

Okay, how about looking at it this way. At the very beginning, you decide how much current you want to put out into 1 Ohm. Say it's 40A. I'll refer to the reference designators in your original mikeks.zip in this post below. So try the following:

1) With a 1 Ohm load, do a sine wave transient sim of output stage, drivers and predrivers only, with appropriate bias at the bases of Q1 and Q2. Drive the output to +/-40V into the 1 Ohm load. That is, apply a little bit more than +/- 40V sine wave to the bases of Q1 and Q2 with DC offset between them.

2) Plot the difference between the output voltage V(Out) and V(Ref_EC) (junction of R1 and R2).

I just tried this (sim attached) and got about +/- 2.4V for the peak value of this difference. Assuming the diff amp's gain is one, that means you'll want to have something like 3 V DC or even more quiescent across R6 and R13. I would think 4V would be enough.

Edit: Oops, I posted this before I saw your reply immediately above.

 

[mikeks]

I just tried this (sim attached) and got about +/- 2.4V for the peak value of this difference. Assuming the diff amp's gain is one, that means you'll want to have something like 3 V DC or even more quiescent across R6 and R13. I would think 4V would be enough.

Good thinking!

Will look at this later today.

Cheers.

 

[powerbecker]

Nevertheless, as indicated here, it would appear impractical to aspire to driving 40V(peak) across 1Ohm without causing the EC loop to go into hard current-clip.

I am now of the view, at least provisionally, that EC loops are best suited to well-defined medium loads, as encountered, for instance, in actively driven 'speaker systems.

No

 

[andy_c]

Re: Re: Controlled clipping of EC amplifiers

(...)anyway it would be better not to use a deep frequency filter, may be better this?

That's a very cool circuit, Heinz. It seems like a nonlinear circuit like what you posted could have some real advantages over simple linear filtering of the supply. Nearly total ripple rejection seems possible.

I probably described what I was looking for rather poorly though. My goal is a Baker clamp for the voltage amplifier stage (VAS) of my amp. This would force it to clip internally at around +/- 85V or so, but variable as the unregulated +/- 90V to the output devices sags under load. This would be like figure 8 in Bob's amp, transistors Q18 and Q19. I'd like to set their base voltages in a way that tracks the unregulated supply to the output devices.

Actually, as I am writing this, some ideas are coming to me. I will have +/- 15V available for DC servo op-amps. So I could make the bias voltage of the Baker clamps shift up and down with the output voltage variation of your circuit. I will have to think about this some more. Nonlinear circuits with op-amps really mess with my mind, so I have to be really careful to make sure I understand them fully.

Thanks again!

 

[powerbecker]

Re: Re: Re: Controlled clipping of EC amplifiers

That's a very cool circuit, Heinz. It seems like a nonlinear circuit like what you posted could have some real advantages over simple linear filtering of the supply. Nearly total ripple rejection seems possible.

I probably described what I was looking for rather poorly though. My goal is a Baker clamp for the voltage amplifier stage (VAS) of my amp. This would force it to clip internally at around +/- 85V or so, but variable as the unregulated +/- 90V to the output devices sags under load. This would be like figure 8 in Bob's amp, transistors Q18 and Q19. I'd like to set their base voltages in a way that tracks the unregulated supply to the output devices.

Actually, as I am writing this, some ideas are coming to me. I will have +/- 15V available for DC servo op-amps. So I could make the bias voltage of the Baker clamps shift up and down with the output voltage variation of your circuit. I will have to think about this some more. Nonlinear circuits with op-amps really mess with my mind, so I have to be really careful to make sure I understand them fully.

Thanks again!

Thank you Andy,

you describe it exactly!
My idea was to use 2 of them (one for +Ub, one for -Ub) as a reference for a "soft" input clamp.
Your idea to amplify it again can bee a bit costly, I have to think, if there is a more direct way to do the same at high voltages.
currently I have no idea!

Heinz!

 

[powerbecker]

Possibly this?

 

[gootee]

Any further useful adjustments will be appreciated.

Mikeks,

I don't know if this will be useful, but...

I ran your mike04.asc (after adding ".include KSA1220A.txt").

I should mention that I noted that the speed of the simulation hinted that there might be some high-frequency simulator artifacts occurring (or else some "real" HF stuff).

I decided to add a squarewave (pulse) input, for -15/+15v, 2.5u rise and fall times, 40u on time, and 85u period, because squarewave results have been much more helpful, to me, in trying to understand EC operation, during simulations, than sinewaves.

The squarewave output was beautiful. But then I added a 0.1uF capacitor (with ESR 0.02 Ohms), in parallel with the 8 Ohm load. The result was less than optimal.

But adding some capacitance across your four 511 Ohm resistors might be a start, in making the squarewave simulations useful. (I don't know how well it might be applicable, for your real hardware. [I'm not really much of a x-istor guy. I just x-ist. 🙂 ]) The squarewave output into 8 Ohms || 0.1uF/.02 Ohms looked pretty decent, with the added capacitors.

About 4700pF (.02 ESR) across each of R6, R13, R24, and R45 seems like a good start. (But the devil is probably in the details, as I've found while trying to compensate and fine-tune simple opamp-based EC circuits.)

I also noted that the simulation ran much, much faster, with those caps added.

- Tom Gootee

 

[mikeks]

......adding some capacitance across your four 511 Ohm resistors might be a start, in making the squarewave simulations useful......4700pF (.02 ESR) across each of R6, R13, R24, and R45 seems like a good start.

I also noted that the simulation ran much, much faster, with those caps added.
Tom Gootee

Hi Tom,

Thanks for your input.

Placing capacitance across the diff. stage's degeneration resistors merely increases gain even as the capacitance across load resistors R6/13 strives to reduce it.

One might conceivably increase capacitance across R6/13 in practice to, say, 220p, to improve local stability margins, but i think you'll find that simulation speed in this case is constrained by the selected time-step in ''transient analysis''. You may, if so desired, reduce this from 1e-8 to 1e-6 to speed up simulation time at the expense of precision.

 

[mikeks]

Hi Andy,

We can expound on your eminently reasonable thinking here by considering that output stage error appears across a common degeneration resistor sandwiched between two base-emitter junctions.

Therefore, if a maximum error of 5V is anticipated, then we would expect to drop roughly 3.8V across the degeneration resistor.

If a 100 Ohm degeneration resistor is used, then the current in this resistor, for a 5V error, would be 38mA, necessitating the use of a standing current >38mA in each BJT in the diff. stage if current clipping is to be avoided. This level of quiescent current is, of course, untenable.

However, If a 511 Ohm degeneration resistor is used instead, the current in this resistor, for the same 5V error, falls to a little under 7.5mA. Thus, the standing current in each BJT in the diff. stage need not exceed 8mA.

Moreover, this circuit possesses the advantage that we need no longer indulge in that linearity compromising attenuation-before-amplification sleight-of-hand, that appears necessary in this arrangement.

In general terms, nevertheless, it is not really reasonable to expect to drive a 1 Ohm load to 40V@20KHz on continuous duty. Any EC loop would be functioning at the boundaries of its linear capability in these circumstances, and, in practice, the output stage requires at least +/-60V supply rails and bus-bars and/or ''hard-wiring'' rather than PCB traces to minimise the influence of parasitic resistance and reactance.

 

[mikeks]

Hi Andy,

I suppose the next step is reducing the loop's sensitivity to component tolerances as discussed in the following posts:

http://www.diyaudio.com/forums/showthread.php?postid=1075966#post1075966

http://www.diyaudio.com/forums/showthread.php?postid=1076363#post1076363

http://www.diyaudio.com/forums/showthread.php?postid=1076508#post1076508

http://www.diyaudio.com/forums/showthread.php?postid=1077326#post1077326

http://www.diyaudio.com/forums/showthread.php?postid=1080345#post1080345

Ideas welcome! 🙂

 

[gootee]

Hi Tom,

Thanks for your input.

Placing capacitance across the diff. stage's degeneration resistors merely increases gain even as the capacitance across load resistors R6/13 strives to reduce it.

One might conceivably increase capacitance across R6/13 in practice to, say, 220p, to improve local stability margins, but i think you'll find that simulation speed in this case is constrained by the selected time-step in ''transient analysis''. You may, if so desired, reduce this from 1e-8 to 1e-6 to speed up simulation time at the expense of precision.

Actually, it wasn't only the speed of the simulation that was worrisome, to me.

My main point of concern was the oscillation at the output, with a squarewave input and a 0.1uF capacitor placed in parallel with the load.

 

[mikeks]

Re: Re: Re: Controlled clipping of EC amplifiers

My goal is a Baker clamp for the voltage amplifier stage (VAS) of my amp.

This would force it to clip internally at around +/- 85V or so, but variable as the unregulated +/- 90V to the output devices sags under load.

This would be like figure 8 in Bob's amp, transistors Q18 and Q19.

I'd like to set their base voltages in a way that tracks the unregulated supply to the output devices.

Hi Andy,

I am not certain that you need to go to all this trouble.

I might well be wrong, but it seems to me that all you require are independent Baker clamps for the second stage and the output stage to ensure that neither ever goes into saturation, regardless of sagging, or lack thereof, of the output stage rails.

 

[mikeks]

My main point of concern was the oscillation at the output, with a squarewave input and a 0.1uF capacitor placed in parallel with the load.

I would expect such oscillation with a capacitive load since Thiel's network is absent from the SPICE model.

 

[mikeks]

Mike, I must strongly disagree with you. I have lost track of which EC circuit you are talking about, but the one I use has absolutely no problem with headroom driving high current into a load. Keep in mind that if you use an appropriate number of MOSFETs in parallel as dictated by the requirements for the rating of the power amplifier, it does not take very much gate drive beyond the gate drive for quiescent bias to drive the devices to very high currents. Look at the curves.
Bob

Sorry, Bob, I missed your post somehow.

Yes, with Andy's help I managed to recover from this erroneous position. 🙂

However, it is now apparent that whether or not your EC loop goes into current clip is a function of the error generated by the output stage, and is, therefore, also a function of the load the output stage is called upon to drive.

 

[mikeks]

For example, you may obtain a SIM. of your EC output stage attempting to drive 1Ohm to 25V(peak) below.

Extracted error (plot V(N007,OUT)) exceeds 10V(peak), and resolutely drives the error loop into current clip; this may be confirmed by plotting Ic(Q5).

 

[Bob Cordell]

Hi Andy,


In general terms, nevertheless, it is not really reasonable to expect to drive a 1 Ohm load to 40V@20KHz on continuous duty. Any EC loop would be functioning at the boundaries of its linear capability in these circumstances, and, in practice, the output stage requires at least +/-60V supply rails and bus-bars and/or ''hard-wiring'' rather than PCB traces to minimise the influence of parasitic resistance and reactance.

Mike,

You insist on making this incorrect generalization. Maybe YOUR EC topology suffers from this limitation, but mine certainly does not. Have you not been paying attention to my explanations on this issue? Look at the IRFP-240 data sheet and do the math. 40-amp peaks are a walk in the park for two MOSFET pairs with only about 2.5V drive beyond the static bias level, and my EC circuit has much more headroom available than this. It sounds to me like you have merely uncovered a reason for not using the topology you have been focusing on.

Cheers,
Bob

 

[Bob Cordell]

For example, you may obtain a SIM. of your EC output stage attempting to drive 1Ohm to 25V(peak) below.

Extracted error (plot V(N007,OUT)) exceeds 10V(peak), and resolutely drives the error loop into current clip; this may be confirmed by plotting Ic(Q5).

Mike,

You are simulating the original design that employed only a single MOSFET pair of 1981 vintage. Re-do the simulation with two IRFP240/9240 MOSFET pairs and see what I mean.

Bob

 

[mikeks]

Hi Bob,

It would appear you wrote this post before reading my earlier response.

Indeed, further investigation into the matter of EC dynamic headroom was encouraged by your admission here that you had never established by measurement whether or not Hawksford's arrangement used in your designs was driven into current clip during heavy current excursions in the output stage:

Mike, these are good questions. I did not confirm by measurement that the EC transistors were not saturated or cut off........
Bob

To return to your argument:

Look at the IRFP-240 data sheet and do the math. 40-amp peaks are a walk in the park for two MOSFET pairs with only about 2.5V drive beyond the static bias level

I am afraid I felt no compelling incentive to do the arithmetic in respect of the drive requirements of your MOSFET output stage on the pedestrian grounds that this had virtually nothing to do with issue at hand.

This because your design uses three cross-coupled complementary emitter followers to provide drive to the MOSFET output stage.

It may be taken as axiomatic, therefore, that, with this complement of drivers, the drive requirements of your MOSFET voltage followers are exceeding irrelevant.

The real issue in practice, as noted here, is the inevitable increase in voltage dropped across parasitic resistances and reactances as your output stage attempts to deliver the demanded 40A to a 1R load in order to swing 40V; these are layout and power supply-dependent, and cannot, therefore, be accurately modelled in SPICE

Clearly, this significant voltage sag is manifest as a substantial increase in the difference between the voltage at the input of your MOSFET follower and its output.

Moreover, this increase in error extracted is vastly greater with MOSFETs than with BJTs; a factor that is not as readily apparent in SPICE as it is in practice.

Thus, far from being an ''incorrect generalisation'', given reasonable standing currents in the EC amplifiers, my assertion here that:

In general terms, nevertheless, it is not really reasonable to expect to drive a 1 Ohm load to 40V@20KHz on continuous duty. Any EC loop would be functioning at the boundaries of its linear capability in these circumstances, and, in practice, the output stage requires at least +/-60V supply rails and bus-bars and/or ''hard-wiring'' rather than PCB traces to minimise the influence of parasitic resistance and reactance.

is correct in fact.

Note, also, that there are three significant differences between Hawksford's arrangement here and my adaptation here:

1. The later arrangement operates as a unity-gain voltage follower while Hawksford must necessarily operate with a gain greater than unity.

2. Hawford uses a single common emitter BJT as error amplifier. A differential amp. is used in mine and Andy_C's adaptation of Yokoyama.

The above suggest that our respective arrangements are superior to Hawksford in respect of EC-loop linearity.

3. Hawksford's arrangement requires that it be preceded by a voltage reference to provide the headroom it requires to operate, but, simultaneously, is itself required to bias the output stage.

This duplication is not necessary in my adaptation.