i've been a bit busy with other projects lately but i'll make some time to do the transient load testing with jbau's latest configuration. i've already built the load switch so it should be easy enough to do. i've done a lot of transient load testing with similar configurations to jbau's latest so i would be really surprised if the results showed any significant oscillation.
i have a thread in the power supply design forum that shows some of the results of my transient load tests.
i have a thread in the power supply design forum that shows some of the results of my transient load tests.
I guess the participants here already know this one, but for others, AppNote AN-104 from Linear by the great Jim Williams has pretty good details on this method:infinia said:
http://cds.linear.com/docs/Application Note/an104f.pdf
I've used this exact setup of Fig.6 a lot at work for small-scale SMPS testing.
BTW: I'm following this thread...
With jbau's results on the LT1085 with the known component values this would a nice check of sim vs reality...
- Klaus
KSTR said:I guess the participants here already know this one, but for others, AppNote AN-104 from Linear by the great Jim Williams has pretty good details on this method:
http://cds.linear.com/docs/Application Note/an104f.pdf
I've used this exact setup of Fig.6 a lot at work for small-scale SMPS testing.
BTW: I'm following this thread...
With jbau's results on the LT1085 with the known component values this would a nice check of sim vs reality...
- Klaus
i've read that app note several times - it was my motivation for making a load switch.
all jbau's results are experimental. do you think he is showing computational/simulation results?
KSTR said:
Very interesting, indeed. Thanks for that.
I'm guessing that further increasing the Cadj to say 1mF would improve the phase lag below 10Hz. But then, it is questionable that would be audible.
Since the 20mOhm Rbuffer appears to the LT1085 as just raising the ESR of the 560uF cap, I'm wondering whether the sim shows significant difference in the Z peaking in the MHz region, with and without it? I would guess not.
Please raise R5 to 40m and it should fill the dip around 10kHz a bit. Maybe even a little higher would be better. Adding some esr for C1 would probably help this region as well.
It all depends on how exact you can match the conjugate impedances, that is Rout+Lout with C and ESR (see my equation a few posts earlier). Much of these variables are not well controlled, the only way to get lower sensivity were to increase Lout (masking part-to-part differences) and increase Rout (to mask intrinic Rout) -- which we already do --, since that R value is the most critical (because it is squared in the matching equation). ESL of the cap is only affecting the final rise and that can be handled.
A very controlled and known behaviour of the used output cap is the main point. Once it is given, the rest (added Lout and Rout or ESR) can be trimmed to get the best results with the actual layout used.
ESR/ESL of the adjust cap is irrelevant. And with the low values of resistors their parasitics also don't matter much. Only the hookup as close as possible is very important. Inductance itself in the control return is also not critical per se (but noise pickup there of course is).
I'll be fiddling a bit and present the optimum values (according to the sim, of course), for a target of say, 30mR max Zout and flattest phase with some typical part and board parasitics assumed.
- Klaus
A very controlled and known behaviour of the used output cap is the main point. Once it is given, the rest (added Lout and Rout or ESR) can be trimmed to get the best results with the actual layout used.
ESR/ESL of the adjust cap is irrelevant. And with the low values of resistors their parasitics also don't matter much. Only the hookup as close as possible is very important. Inductance itself in the control return is also not critical per se (but noise pickup there of course is).
I'll be fiddling a bit and present the optimum values (according to the sim, of course), for a target of say, 30mR max Zout and flattest phase with some typical part and board parasitics assumed.
- Klaus
KSTR said:
And of course most circuits WILL have shunt C's at the devices... but that's another bag of worms, though closely related.
Your findings generally mirror what my experiments have shown, especially the dominant influence of the Rbuffer value. All other reactive interactions pivot around that + the reg's inherent Rout and Lout.
It's a good thing our hearing craps out before 20kHz, because getting low and linear Z/phase above that would be a real pain!
Hi,
with a bit of tweaking I can get a flat Zout of 23mR and +-1deg phase variation from 10Hz to xxxkHz, xxx depening on the ESL, which can be cancelled with the same trick we used to cancel the Lout of the reg.
This is computer gaming of course, that sweet spot is very sensitive, especially on I-out. So even when that op point could be dialed in it would only be perfect with constant current draw from the load.
The values, anyway: R_buffer=20mR, L_buffer 2.7uH//10R, C=5700uF, ESR=23mR, ESL=xxx, C_adj=1000uF (this could be optimized by buffering the adjust pin with an emitter-follower).
----
Board trace tempco, if properly designed? I found it a non-issue, compared to the deviation of such an R from process changes, switching to another board-house etc.
In fact we would need a tracking resistance to the changing ESR of the output cap -- or proper bypasses and the delibate ESR added.
I'd say, sticking to the ballpark values that jbau has found should do it, if one needs a better mid-band perfomance then other means are in charge. If we add some L_buffer, the output cap needs to get bigger, btw
For example I get flattest result, given a 1000uF, 23mR-ESL were used, with an L_buffer of 330nH
- Klaus
with a bit of tweaking I can get a flat Zout of 23mR and +-1deg phase variation from 10Hz to xxxkHz, xxx depening on the ESL, which can be cancelled with the same trick we used to cancel the Lout of the reg.
This is computer gaming of course, that sweet spot is very sensitive, especially on I-out. So even when that op point could be dialed in it would only be perfect with constant current draw from the load.
The values, anyway: R_buffer=20mR, L_buffer 2.7uH//10R, C=5700uF, ESR=23mR, ESL=xxx, C_adj=1000uF (this could be optimized by buffering the adjust pin with an emitter-follower).
----
Board trace tempco, if properly designed? I found it a non-issue, compared to the deviation of such an R from process changes, switching to another board-house etc.
In fact we would need a tracking resistance to the changing ESR of the output cap -- or proper bypasses and the delibate ESR added.
I'd say, sticking to the ballpark values that jbau has found should do it, if one needs a better mid-band perfomance then other means are in charge. If we add some L_buffer, the output cap needs to get bigger, btw
For example I get flattest result, given a 1000uF, 23mR-ESL were used, with an L_buffer of 330nH
- Klaus
KSTR said:
Good stuff, thanks. Please put up a plot of that optimization if you could. Also, please clarify where you have the "L_buffer 2.7uH//10R" in the model, it would be right at the output before the 100R adjust resistor, yes?
One of the things I was going to play with was replacing the 20mR Rbuffer with a winding of 6" of 26 ga wire around a 0.1R resistor body, which gives the needed 20mR value plus some L to further isolate the load. I already wound it but don't remember what the L measured. But you're right, the Cout would have to be larger and then reactive interactions (i.e. component tolerances) become more sensitive. All other things being equal, I'd favor the solution with the smaller Cout.
No, it's after the basic regulator. See attachment. But it doesn't matter much, it is not important from where the current comes to establish the DC voltage drop to set the output voltage. A low impedance at the adj pin is needed to make the transient change of current out of that pin irrelevant for the regulation.jbau said:
That would work, too. The 10R was just a shot from the hip. Maybe 0.1R is still a bit low, point is that it is harder to get the exact conjugate since this introduces a transition between the reg's L_out and and the sum of reg L_out + buffer L_out. This disturbes the simple L+R output impedance, assuming that the reg output is indeed truly inductive until it flattens out again to about 6R of open loop Zout at ~60mA total output current draw, which again is directly related to the transconductance of the series transistor.OTOH this kink in Zout is at rather high frequencies (~100kHz) so probaby that's not important that much. Another way to lower C_out is to increase the R_out design goal, if that is suitable. Doubling this value lowers C_out to 1/4.
- Klaus
Attachments
BTW, this is very interresting, albeit more for the SMPS crowd:
http://www.diyhifi.org/forums/viewtopic.php?p=15194#p15194
http://www.diyhifi.org/forums/viewtopic.php?p=15194#p15194
I have some 47uF MLC caps that should push ESR down wideband
http://www.novacap.com/pdfs/HCV.pdf
http://www.novacap.com/pdfs/HCV.pdf
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