The AD1955 might be worth a quick look, as it is at least competitive with PCM1794A and has a better datasheet in terms of performance characterization. It still doesn't cover your high sample rate needs and it has a 5V digital supply, which will be annoying.
It's probably not worse than CS43198 for instrumentation, though. The CS43198 datasheet does not inspire confidence if you are looking for top performance at >= 192 kHz. Enabling the wideband flatness mode has a bit of a distortion penalty and the filter responses are not amazing.
It's probably not worse than CS43198 for instrumentation, though. The CS43198 datasheet does not inspire confidence if you are looking for top performance at >= 192 kHz. Enabling the wideband flatness mode has a bit of a distortion penalty and the filter responses are not amazing.
As I see on your board, the master clock of the ADC PCB is given from a separated PCM over a isolation (= jittery) chip... so phase noise of you clock distribution will be hardly reduced...
Or I am wrong..??
Hp
Isolators introduce little additive jitter, but mostly a delay in the nS range. In particular, the Si8661 150Mb/s digital isolator has a datasheet guaranteed 350pS peak, eye diagram, additive jitter. How much that matters, you can estimate from the measurements shown above.
"Clock jitter" could be a problem mostly for high speed ADCs, where high slew rate signals coupled with the jitter aperture of the sampling clock are introducing a random variation (aka "noise") in the amplitude of the acquired signal. A 20KHz signal has a slew rate of max. 0.3V/uS which in 350pS results in a peak-to-peak noise of about 100uV, or a RMS noise of 12uV. This is a degradation of the SNR of about -110dB, which is already well under the ADC chip SNR performance at that frequency (I wish I had an ADC with 110dB SNR performance at 20KHz and 192/384KHz sampling rate). And the above are the absolute worst case values. And the fact that delta-sigma converters do not use the master clock to sample the input signal, like the SAR converters do, check this AD white paper: Sigma-Delta ADC Clocking—More Than Jitter | Analog Devices
Bottom line, stop obsessing over "jitter" when it comes to audio frequencies, it's yet another red herring promoted by those with an agenda to sell your nicely packed bull chips. 1pS jitter for audio, what a joke, to those claiming they can hear a 350pS jitter, tell them I don't care, I don't listen through instruments.
"Clock jitter" could be a problem mostly for high speed ADCs, where high slew rate signals coupled with the jitter aperture of the sampling clock are introducing a random variation (aka "noise") in the amplitude of the acquired signal. A 20KHz signal has a slew rate of max. 0.3V/uS which in 350pS results in a peak-to-peak noise of about 100uV, or a RMS noise of 12uV. This is a degradation of the SNR of about -110dB, which is already well under the ADC chip SNR performance at that frequency (I wish I had an ADC with 110dB SNR performance at 20KHz and 192/384KHz sampling rate). And the above are the absolute worst case values. And the fact that delta-sigma converters do not use the master clock to sample the input signal, like the SAR converters do, check this AD white paper: Sigma-Delta ADC Clocking—More Than Jitter | Analog Devices
Bottom line, stop obsessing over "jitter" when it comes to audio frequencies, it's yet another red herring promoted by those with an agenda to sell your nicely packed bull chips. 1pS jitter for audio, what a joke, to those claiming they can hear a 350pS jitter, tell them I don't care, I don't listen through instruments.
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I'm a little confused by the concept of an SNR at a specific frequency. Maybe you can explain further? I usually understand SNR to have a bandwidth more than a specific frequency. If you are saying 110 dB SNR at unweighted 0-96KHz/0-192KHz bandwidth I can relate.
I have never been clear how to quantify clock jitter on the output of an ADC. It works differently from a DAC it seems. I have seen significant reduction in noise and THD from an improved clock on the AK5394A. But that was just basic execution quality issues I thought.
It seems counterintuitive from an audio perspective, but I think this article does a good job of explaining it: https://www.analog.com/media/en/reference-design-documentation/design-notes/dn1013f.pdf
That’s what I meant, plus the internal issues of the ADC. HF signals have high slew rates, therefore the amount of pp noise at the output increases with frequency, degrading the SNR.
In a first order approximation, you have a bandwidth limited signal, say a sine at the fs/2 Nyquist frequency. This sine has a max slew rate at the zero crossings of 2*pi*f*V. Multiply this by the jitter J and you’ll get the peak-to-peak noise at the output. Divide this by ~8 and you’ll get the output RMS noise. All together makes a SNR of dB(4/(pi*f*J)). Say f=1MHz, jitter 10pS, you’ll get a SNR contribution of about 100dB. This applies for a SAR ADC where the noise is defined strictly at the sampling moment, for a delta sigma I don’t know, but intuitively I don’t see any reason why it should be much different.
Jitter becomes a serious problem for high speed ADCs, at audio frequencies is a non issue.
The SNR is only one aspect of the effect of the clock noise. In a first approximation you get as output of the DAC the convolution of the clock with the input signal, see https://www.analog.com/media/en/training-seminars/tutorials/MT-008.pdf.
The broad band phase noise reduces the SNR. The close in phase noise the frequency resolution.
Moreover as the jitter distribution is not Gaussian the RMS-jitter-noise, e.g. the variance, does not contain the full information of the jitter distribution.
The broad band phase noise reduces the SNR. The close in phase noise the frequency resolution.
Moreover as the jitter distribution is not Gaussian the RMS-jitter-noise, e.g. the variance, does not contain the full information of the jitter distribution.
Not sure I follow, what would be other aspects of the effect of clock [phase] noise, beyond SNR?
Non Gaussian noise is correlated noise, so treating it as gaussian noise actually overestimates it's effect on the SNR, since only uncorrelated noise sources add squared. Hence, no engineering problem to address here.
Yes there are effects. E.g. that if the close in phase noise of the clock is "high", you can get from an perfect sine input no sharp spike in the FFT, regardless the FFT size or the ADC quality - you will see the clock distribution. The linked PDFs main topic is something else but there are nice infos in that direction in-between.
As mostly the RMS jitter is given for the "standard" integration bandwidth 12 kHz to 20 MHz, it contains no contribution of the close in part. You can thus not estimate it. Here the linked PDF is a good reading.
I'm sorry, it must be me, but I don't understand a d*mn thing of what you are trying to convey here. No idea what "close in phase noise", "sharp spike in the FFT", "standard" integration bandwidth 12 kHz to 20 MHz" all are.
The relationship between the phase noise and jitter is texbook since shortly after WWII, and so is the jitter effect on the FFT distribution at the fundamental and around harmonics. Same as any other type of additive noise, it's of no practical relevance, since only a smaller FFT bin size is required.
PCM1794 / 1792 support at least 768k but you have to disable internal DF. 1792 is probably better bet as it has a few more configurable parameters
accessible via software such as modulator speed. Probably best in mono mode, you can also tweak the power supplies (DDDAC has been running 8V
for years) and I ref.
I've seen a few 1792 implementations that get everything around -130dB at 0dBFS but they are finicky and will easily give you 30dB worse which what
most people seem to achieve. Maybe it's the CCS OP architecture, not sure.
I think all these DACs are capable of really low measured distortion but it just takes some tweaking.
TCD
Let's say I would like to generate a 200kHz sine signal to sample with the 512kHz ADS127L01. If I circumvent the internal DF of PCM179x and feed it with a 512kHz samplerate signal directly, what level of oversampling can the DAC provide so that the analog reconstruction filter is practically feasible? Thanks a lot.
There are voices raised that the very low frequency (0-10 Hz) sideband of the used oscillator has a real negative impact on both ADC as well as DAC. The "close-in" term means "close to the carrier" i.e. phase noise components of a few Hz - hence "close-in". High end oscs exhibit say -125 dBc/Hz at 1 Hz i.e. a very clean carrier.
The 12-20k "thing" is that most oscillators existing now are derived from the telecom era and the standard specification describing jitter/phase noise in that band and close-in was of no importance to these applications. It does make a difference in the very tight rf coding in mobile systems and is there a real world performance issue. I have chased dropped calls due to passing trains in base stations exposed to vibration in my days
Hope that helped a bit
//
@syn08
I suggest to convince yourself by doing it as experiment yourself.
Replace the ADC clock by a signal generator, shape the phase-noise distribution of that "clock" bad enough and see the effect on the output of your ADC.
P.S. the "sharp spike in the FFT" stuff was aimed as a illustration of the previously claimed reduction of the frequency resolution. And the "12 kHz to 20 MHz" is what you see in the fine print of most clock data sheets when it comes to RMS-jitter.
P.P.S. have you read the attached PDF? It is only a few pages and several of your questions should be answered there by "authorities".
I suggest to convince yourself by doing it as experiment yourself.
Replace the ADC clock by a signal generator, shape the phase-noise distribution of that "clock" bad enough and see the effect on the output of your ADC.
P.S. the "sharp spike in the FFT" stuff was aimed as a illustration of the previously claimed reduction of the frequency resolution. And the "12 kHz to 20 MHz" is what you see in the fine print of most clock data sheets when it comes to RMS-jitter.
P.P.S. have you read the attached PDF? It is only a few pages and several of your questions should be answered there by "authorities".
I'm not really sure what you mean by practically feasible. Clearly the 1794 is optimised for 384kHz as distortion is lowest with 48kHz IP (x 8 int DF).
So probably the 1792 is a better bet with the option to tun modulator up
to 12.288MHz at 16 x (96 x 8).
Having said all this, the 1794 / 2 do have fairly high OOB noise so may not
be your best option for such a high freq. AKM have much flatter OOB noise.
TCD
The fact is I really do not understand the datasheet section talking about the external filter.
For a 200kHz analog signal the analog reconstruction filter should have its cutoff frequency above 200kHz, while decently attenuating at the real Nyquist freq. That would require I guess at least 8x oversampling for 512kHz to keep the analog filter at a resonable order. I do not know if that 192kHz DAC is capable of that.
P41, PCM1792A data sheet. Yes it is confusing.
But as stated, AKM much more likely to be a better option for 200kHz.
TCD
But what is the Fs at that scenario? 512kHz samplerate into the external filter input - what should the WDCK be? The datasheet says "The word (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, fs" - but what is the "desired sampling frequency"? Then I guess OS selected at 8xWDCK should set the real Nyquist at 2MHz, correct? Still only 8x oversampling, not much for the reconstruction filter. Thanks.
Well, that remains to be tested, I have not seen any performance measurements of the AKM DACs in these high-frequency ranges. I hope to learn more in some weeks when my DAC testing rig hooked to RPi4 is finished.
Well, that remains to be tested, I have not seen any performance measurements of the AKM DACs in these high-frequency ranges. I hope to learn more in some weeks when my DAC testing rig hooked to RPi4 is finished.