Graham,
Aha, thanks, I see my mistake and have re-uploaded the picture
http://gaydenko.com/ab-dynamic/back-emf-sweep59.png
with the same name (please, hit "reload"). Now voltage was seen at the same point, i.e., after a choke. It seems, now curves are not such nice, are they?
I'll try 10KHz fragment and report.
Aha, thanks, I see my mistake and have re-uploaded the picture
http://gaydenko.com/ab-dynamic/back-emf-sweep59.png
with the same name (please, hit "reload"). Now voltage was seen at the same point, i.e., after a choke. It seems, now curves are not such nice, are they?
I'll try 10KHz fragment and report.
Graham Maynard said:
Graham,
It is here:
http://gaydenko.com/ab-dynamic/delay10KHz59.png
For positive start and a negative start as for different DC offsets results look similar.
And the same without choke:
http://gaydenko.com/ab-dynamic/delay10KHz-withoutChoke59.png
Okay.
The choke shows leading voltage development at the output terminal.
This can be caused by crossover circuitry, and then distort treble drive appearing at the amplifier's output terminal.
Some ribbon users prefer direct SS very low impedance drive to using a transformer due to the 'transformer inductance' generated effect.
Direct connection shows nicely coherent damping.
But tell me. Why does your trace start after 1mS ?
This allows your amplifier to stabilise for steady sine.
If there were any internal or global NFB loop *induced* errors arising within the first cycle then you have already missed them !!!
Observing the first couple of microseconds is essential.
Semiconductor amplifiers are capable of responding within 100nS in the forward direction, but NFB loops and stabilisation circuitry can seriously delay output terminal control/correction.
Looking at your 'without choke' trace, the full cycle zero crossover occurs closer to 90uS than 100uS in repeat cycle time.
This means that there was reaction within the first cycle.
The amplifier did not respond instantly, so a minute error would have developed, which would then have been corrected. This correction relates to internal phase change due to the number of devices and their connection, also the way the internal open loop characteristics have been modified by global setting components and stabilisation components.
Steady sine examination at the output terminal in time isolation does not show the real problems. Every sine at the output terminal could have ultra low distortion, but they might all crossover at different points along the time axis and thus there will be fractional voltage errors wrt say the 1kHz zero crossovers normally taken as reference.
To get an idea of how correct the amplifier will 'sound', that first cycle reaction where the zero crossovers become shifted in time needs to be observed. A zero crossover shift (group delay variation) in time = voltage amplitude error wrt source waveform (distortion).
Next. I would run this test for full rail-rail amplitude at lowest R to be expected, to check that biasing/drive capabilities cannot be exceeded. Sometimes an unexpected error can be seen developing at a particular threshold.
Anli. Is this a real world circuit, or merely a simulation exercise ?
Cheers ......... Graham.
The choke shows leading voltage development at the output terminal.
This can be caused by crossover circuitry, and then distort treble drive appearing at the amplifier's output terminal.
Some ribbon users prefer direct SS very low impedance drive to using a transformer due to the 'transformer inductance' generated effect.
Direct connection shows nicely coherent damping.
But tell me. Why does your trace start after 1mS ?
This allows your amplifier to stabilise for steady sine.
If there were any internal or global NFB loop *induced* errors arising within the first cycle then you have already missed them !!!
Observing the first couple of microseconds is essential.
Semiconductor amplifiers are capable of responding within 100nS in the forward direction, but NFB loops and stabilisation circuitry can seriously delay output terminal control/correction.
Looking at your 'without choke' trace, the full cycle zero crossover occurs closer to 90uS than 100uS in repeat cycle time.
This means that there was reaction within the first cycle.
The amplifier did not respond instantly, so a minute error would have developed, which would then have been corrected. This correction relates to internal phase change due to the number of devices and their connection, also the way the internal open loop characteristics have been modified by global setting components and stabilisation components.
Steady sine examination at the output terminal in time isolation does not show the real problems. Every sine at the output terminal could have ultra low distortion, but they might all crossover at different points along the time axis and thus there will be fractional voltage errors wrt say the 1kHz zero crossovers normally taken as reference.
To get an idea of how correct the amplifier will 'sound', that first cycle reaction where the zero crossovers become shifted in time needs to be observed. A zero crossover shift (group delay variation) in time = voltage amplitude error wrt source waveform (distortion).
Next. I would run this test for full rail-rail amplitude at lowest R to be expected, to check that biasing/drive capabilities cannot be exceeded. Sometimes an unexpected error can be seen developing at a particular threshold.
Anli. Is this a real world circuit, or merely a simulation exercise ?
Cheers ......... Graham.
Graham,
Everywhere I say about simulating the project. I have mentioned earlier, ordered parts are arrived partially yet.
As for 1mS delay - at any case simulator calculates an operation point, so delay was introduced to make observing more handy. It is similar as we have turned the app on and after 1mS we have turned on LF signal sources.
I don't see any time shift for without-choke-case. I have mentioned, this was measured for different DC shifts at input. 1ms delay helps to see where "virtual zero" level takes place. And there are no any time shifts against this "zero".
As for with-choke-case, the visible artifact for first sine period is simply a choke influence and would be the same with grounded other choke pin (i.e. an amp output).
Have I missed something?
Everywhere I say about simulating the project. I have mentioned earlier, ordered parts are arrived partially yet.
As for 1mS delay - at any case simulator calculates an operation point, so delay was introduced to make observing more handy. It is similar as we have turned the app on and after 1mS we have turned on LF signal sources.
I don't see any time shift for without-choke-case. I have mentioned, this was measured for different DC shifts at input. 1ms delay helps to see where "virtual zero" level takes place. And there are no any time shifts against this "zero".
As for with-choke-case, the visible artifact for first sine period is simply a choke influence and would be the same with grounded other choke pin (i.e. an amp output).
Have I missed something?
Okay, so a the start is delayed, not just recording. Thus the damping shown looks good, and much superior to many bipolar responses. Thus I wonder about iteration and resolution.
Is there any way that your window could be altered to see what happens during the first half cycle, more especially the first few microseconds ?
I wish you luck for the circuit working in real life, but I do have concerns - eg;-
Q1 bootstrapping J1 with an R4+C2 between and C4 to output.
Your NFB path is a X1+Q3 cascode with X2 current gain. There is nothing to prevent X2 overdriving and destroying M2 in the event of inadvertent output short circuit.
Voltage balance betwee J2 and X1 must be trimmed to establish output zero. Can your simulator run through a temperature range to check output drift.
Cheers ......... Graham.
Is there any way that your window could be altered to see what happens during the first half cycle, more especially the first few microseconds ?
I wish you luck for the circuit working in real life, but I do have concerns - eg;-
Q1 bootstrapping J1 with an R4+C2 between and C4 to output.
Your NFB path is a X1+Q3 cascode with X2 current gain. There is nothing to prevent X2 overdriving and destroying M2 in the event of inadvertent output short circuit.
Voltage balance betwee J2 and X1 must be trimmed to establish output zero. Can your simulator run through a temperature range to check output drift.
Cheers ......... Graham.
Graham,Graham Maynard said:
If we look at values on Y-axis, we can see there is digital simulation limit for voltage, it is impossible further zooming, analog signal becomes digital steps.
As the design aim is a home careful use, I'm going to use fuses in PS rails and zeners in gate chains as the only safers.Graham Maynard said:
I have tested (simulated) thermo-stability (for all except for mosfets warming, and for mosfets warming only) - currents and output drift are inside ranges I treat as acceptable.Graham Maynard said:
The process:
http://gaydenko.com/ab-dynamic/pcb/process01.jpg
http://gaydenko.com/ab-dynamic/pcb/process02.jpg
This (slightly modified) variant was selected at last:
http://gaydenko.com/ab-dynamic/schematics55.png
http://gaydenko.com/ab-dynamic/pcb/process01.jpg
http://gaydenko.com/ab-dynamic/pcb/process02.jpg
This (slightly modified) variant was selected at last:
http://gaydenko.com/ab-dynamic/schematics55.png
lumanauw said:
The thing is it's a complete amplifier with gain ~11 - look at R7/R5 here: http://gaydenko.com/ab-dynamic/schematics55.png
death of class A
OK, probably it is a time to share my impressions of this AB-dynamic amplifier. I have called it for me as a "death of class A". The thing is, I have a reference (for me) amplifier with which new one was compared. This reference amp is a bridged, symmetrical (against power rails) class A amplifier (i.e., with a constant PS current consuming). If you can read schematics and is interested in this amp, you can dig in here:
- gain amp (without global NFB): http://gaydenko.com/preamp/final.jpg - look at R3 on block-schematics. This way signal inversion is achieved, needed for bridged topology.
- gain amp's PS regulator - original schematics with symmetrical turning on: http://gaydenko.com/ps60/ps.png (also not patented )
- soft start for the whole amp: http://gaydenko.com/um/ps/softStart-03.png
- follower (with short global NFB and memory distortions elimination): http://gaydenko.com/um/schematics18.png (simplified, real schematics has also chains for smooth mosfets current turning on and triggered turning off, as shown here http://gaydenko.com/um/pcb/schematics.png - left part).
Well, AB-dynamic sounds _slightly_ better than the cited class-A-colossus. Recognized-by-brain difference is a more explicit phrasing at LF (servo absence is a possible reason). All other differences are beyond words (my ones or from other listeners) - simply "better" And, again, a total difference is rather small.
As a result, this AB-dynamic is my "main amplifier" now.
OK, probably it is a time to share my impressions of this AB-dynamic amplifier. I have called it for me as a "death of class A". The thing is, I have a reference (for me) amplifier with which new one was compared. This reference amp is a bridged, symmetrical (against power rails) class A amplifier (i.e., with a constant PS current consuming). If you can read schematics and is interested in this amp, you can dig in here:
- gain amp (without global NFB): http://gaydenko.com/preamp/final.jpg - look at R3 on block-schematics. This way signal inversion is achieved, needed for bridged topology.
- gain amp's PS regulator - original schematics with symmetrical turning on: http://gaydenko.com/ps60/ps.png (also not patented
)- soft start for the whole amp: http://gaydenko.com/um/ps/softStart-03.png
- follower (with short global NFB and memory distortions elimination): http://gaydenko.com/um/schematics18.png (simplified, real schematics has also chains for smooth mosfets current turning on and triggered turning off, as shown here http://gaydenko.com/um/pcb/schematics.png - left part).
Well, AB-dynamic sounds _slightly_ better than the cited class-A-colossus. Recognized-by-brain difference is a more explicit phrasing at LF (servo absence is a possible reason). All other differences are beyond words (my ones or from other listeners) - simply "better"
And, again, a total difference is rather small.As a result, this AB-dynamic is my "main amplifier" now.
Re: Re: death of class A
Also note, if we say about this pcb-related schematics case
http://gaydenko.com/ab-dynamic/pcb/AllToSee.pdf which corresponds to pcb http://gaydenko.com/ab-dynamic/pcb/toPrint.ps
C4 is eliminated, R6 has two places on pcb, R12 has three ones. Of course, additional pcb-places are for tuning. Set with R6-1,R6-2 output voltage about +40mV for cold amp, and with R12-1,R12-2,R12-3 set R16 current about 210mA (also for hold amp).
Try to use similar jfets for both channels with Id(Vgs=0) about 1.5-2mA.
If you have "soft" PS (with noticeable output impedance), you can reduce R11 and R3 down to 2.4K. Real values for soldered amp are shown here: http://gaydenko.com/ab-dynamic/pcb/schematicsReality.png
Bjts has betta value inside their names (say, X1_465) - don't follow them, I have added bettas for hystory only
X1-X4 are 2SC970BL/2SA2240BL. I have used 2SB1109 on Q1,Q2 places as thees bjts (2SB1109/2SD1609) have extremely low Ic dependence from Vce.
Probably it may be interesting for you: I have tried to load the amp with parallel R=5.4 Ohm || C = 100 nF without any negative results.padamiecki said:
Also note, if we say about this pcb-related schematics case
http://gaydenko.com/ab-dynamic/pcb/AllToSee.pdf which corresponds to pcb http://gaydenko.com/ab-dynamic/pcb/toPrint.ps
C4 is eliminated, R6 has two places on pcb, R12 has three ones. Of course, additional pcb-places are for tuning. Set with R6-1,R6-2 output voltage about +40mV for cold amp, and with R12-1,R12-2,R12-3 set R16 current about 210mA (also for hold amp).
Try to use similar jfets for both channels with Id(Vgs=0) about 1.5-2mA.
If you have "soft" PS (with noticeable output impedance), you can reduce R11 and R3 down to 2.4K. Real values for soldered amp are shown here: http://gaydenko.com/ab-dynamic/pcb/schematicsReality.png
Bjts has betta value inside their names (say, X1_465) - don't follow them, I have added bettas for hystory only
X1-X4 are 2SC970BL/2SA2240BL. I have used 2SB1109 on Q1,Q2 places as thees bjts (2SB1109/2SD1609) have extremely low Ic dependence from Vce.
Thanks!juma said:
Currently I have the only loudspeakers which have impedance minimum about 6.7 Ohm (and, as have described, I have tried to load with parallel 5.4 Ohm and 100nF). So, low resistance load was simulated only (say, 2.7 Ohm for schematics55).juma said:
The amp, I hope, has not redundant parts (it was one of the aim)
, so it is easy to prototype and listen to. The http://gaydenko.com/ab-dynamic/pcb/AllToSee.pdf document has schematics variant (eliminate C4 from it) which is almost the same as schematics55 is, but rearranged in "solder-friendly" manner.- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.