The major difference between the SIT3X OS topology and that of the SIT-3 (ignoring the electrolytic capacitor trick) is the SIT3X attenuates the input to the PFET to adjust its contribution to the summed output, whereas the SIT-5 degenerates the PFET to adjust its contribution.
These approaches produce very similar output, however SIT and PFET current waveforms can be quite different, depending of the X-pot setting.
Note that in my schematic:
These approaches produce very similar output, however SIT and PFET current waveforms can be quite different, depending of the X-pot setting.
Note that in my schematic:
- If the Xpot setting is max, it becomes the SIT-5, adjusted by R2.
- If R2=0, is becomes the SIT-3X adjusted by the X-pot.
In my case with the OS I am using I measure the ac current through the sit.
I connect to the amp output a 8r load in series with a dmm set to measure ac current. I adjust the input signal until I get 0.3amps ac.
Then I measure the ac voltage on the modulation resistor. Using ohm law I convert the ac voltage to ac current.
Then I divide the current I get to the output current. Multiply by 100 and you have the percentage.
In your case with the sit 5 Os you will measure the ac voltage on the bigger value resistor that is in series with the cap. After doing the math for the current you will have the mos ac current contribution.
Yes, nice stuff to play with. I like adjustability and this kind of approach of doing big changes with a trimmer.
With a few trimmers and a fft analyzer one can have a lot to explore with these sits.
I was thinking these days that to tune at its best a sit its best to have a fft analyzer.
With these single rail(ac coupled amps) sit amps you have another advantage. With an adjustment for the sit vds you can tune it even further since the output doesn’t need to be at 1/2vcc to get the best performance.
With the above os I experienced that I had to increase the vds on the mos to be >1/2vcc to get rid of the higher order harmonics close to clipping that were generated by the mosfet.
Hi generg, you have to answer this question yourself.
I'm actually just missing the model for LTSpice from the IXTN40P50P.
Maybe someone else can provide this data.
I would be very happy.
Thx
Sorry!
.model IXTN40P50PV VDMOS(pchan Vto=-3.0 Kp=7.42 Lambda=2.9m
you need more?
.model IXTN40P50PV VDMOS(pchan Vto=-3.0 Kp=7.42 Lambda=2.9m
- Rs=2.2m Rd=0.23 Rds=1e7 Cgdmax=6n Cgdmin=90p a=0.26 Cgs=10nF
- Cjo=8.35nF m=0.68 VJ=2.5 IS=4.0E-06 N=2.4 ksubthres=.22))
you need more?
I have some models, if I remember right it was lhquam who gave them to me....
.SUBCKT THF51S 1 2 3 ; Drain Gate Source
+ PARAMS: MU=19.4880 EX=1.204 KG1=0.7031 KP=81.0 KVB=42.0 VCT=2.0 RGI=1MEG
*--------------------------------------------------
E1 7 0 VALUE={V(1,3)/KP*LN(1+EXP(KP*(1/MU+(VCT+V(2,3))/SQRT(KVB+V(1,3)*V(1,3)))))}
RE1 7 0 1G
G1 1 3 VALUE={(PWR(V(7),EX)+PWRS(V(7),EX))/KG1}
RDS 1 3 1G ; TO AVOID FLOATING NODES
D1 5 2 DX ; FOR GRID CURRENT
R1 5 3 {RGI} ; POSITIVE GRID CURRENT
.MODEL DX D(IS=1N RS=1 CJO=10PF TT=1N)
.ENDS
.SUBCKT thf51-1x0063 D G S ; Drain Gate Source
+ PARAMS: MU=43.571 X=1.494 K=1.339 N=0.902 VCT=0.831 RG=5MEG
*--------------------------------------------------
B1 D S I=K*PWR(URAMP((V(G,S)+VCT)+(N*LN(V(D,S))+(V(D,S)/MU))),X)
FOR MULTISIM COMMENT OUT ABOVE LINE () AND UNCOMMENT NEXT LINE
*B1 D S I=K*PWR(MAX((V(G,S)+VCT)+(N*LN(V(D,S))+(V(D,S)/MU)),0),X)
R1 G S {RG}
CGS G S 5000P
CGD G D 5000P
CDS G S 0P
.ENDS thf51-1x0063
they deliver slightly different results
.SUBCKT THF51S 1 2 3 ; Drain Gate Source
+ PARAMS: MU=19.4880 EX=1.204 KG1=0.7031 KP=81.0 KVB=42.0 VCT=2.0 RGI=1MEG
*--------------------------------------------------
E1 7 0 VALUE={V(1,3)/KP*LN(1+EXP(KP*(1/MU+(VCT+V(2,3))/SQRT(KVB+V(1,3)*V(1,3)))))}
RE1 7 0 1G
G1 1 3 VALUE={(PWR(V(7),EX)+PWRS(V(7),EX))/KG1}
RDS 1 3 1G ; TO AVOID FLOATING NODES
D1 5 2 DX ; FOR GRID CURRENT
R1 5 3 {RGI} ; POSITIVE GRID CURRENT
.MODEL DX D(IS=1N RS=1 CJO=10PF TT=1N)
.ENDS
.SUBCKT thf51-1x0063 D G S ; Drain Gate Source
+ PARAMS: MU=43.571 X=1.494 K=1.339 N=0.902 VCT=0.831 RG=5MEG
*--------------------------------------------------
B1 D S I=K*PWR(URAMP((V(G,S)+VCT)+(N*LN(V(D,S))+(V(D,S)/MU))),X)
FOR MULTISIM COMMENT OUT ABOVE LINE () AND UNCOMMENT NEXT LINE
*B1 D S I=K*PWR(MAX((V(G,S)+VCT)+(N*LN(V(D,S))+(V(D,S)/MU)),0),X)
R1 G S {RG}
CGS G S 5000P
CGD G D 5000P
CDS G S 0P
.ENDS thf51-1x0063
they deliver slightly different results
A single rail design with your ps boards and a lipo is another great thing about this design……
When you speak about lipos you want a bms too 🙂
I have a 52v/3.3kw battery that I plan to use with the sit os. Its just waiting there.. it has a bms too.
I have a 52v/3.3kw battery that I plan to use with the sit os. Its just waiting there.. it has a bms too.
Here are some interesting extrapolations of the SIT-5 output stage:
- No need for bias servos.
- Transistors can be undegenerated (SIT-3X style)
- Can combine multiple stages of same or different types.
Happy New Year to everybody!
With the bridged version you have more adjustments to tune the level and phase of h2 but the amp will se 1/2 of the load which is kinda tough with low loads and no global feedback even with a square law os.
When you need a low noise power source the batteries are very good and beside this I developed my own bms so the batteries were needed.
I have many 12s/2ah modules that I plan to use in series to power a sort of preamp(ss or valve). I can control up tu 120s(which is ~500v when fully charged)
Since the fun here never ends..the battery preamp will have to wait a bit more.
For now I am glad that I can listen to a sit amp powered by batteries.
I did listen to a battery powered sit os in the past(the Warbler) but it was at only 12v and there wasn’t so much output power. Instead it sounded nice.
I like the parallel one where each amp sees double the impedance of the load.
With the bridged version you have more adjustments to tune the level and phase of h2 but the amp will se 1/2 of the load which is kinda tough with low loads and no global feedback even with a square law os.
Battery management system.
When you need a low noise power source the batteries are very good and beside this I developed my own bms so the batteries were needed.
I have many 12s/2ah modules that I plan to use in series to power a sort of preamp(ss or valve). I can control up tu 120s(which is ~500v when fully charged)
Since the fun here never ends..the battery preamp will have to wait a bit more.
For now I am glad that I can listen to a sit amp powered by batteries.
I did listen to a battery powered sit os in the past(the Warbler) but it was at only 12v and there wasn’t so much output power. Instead it sounded nice.
:--
.model IXTN40P50PV VDMOS(pchan Vto=-3.0 Kp=7.42 Lambda=2.9m
- Rs=2.2m Rd=0.23 Rds=1e7 Cgdmax=6n Cgdmin=90p a=0.26 Cgs=10nF
- Cjo=8.35nF m=0.68 VJ=2.5 IS=4.0E-06 N=2.4 ksubthres=.22))
made a small mistake here, you need to calculate the ac current through both resistors and then make the sum to find the mos contribution.
You still need that to see the total current through the load.
You can use series connected dmm that measures ac current or you can measure the ac voltage on the load resistor and compute the current value. As like for the other 2 resistors.
I used the dmm on 10A scale which added 0.3r in series with the load so there will be a small error.
I did it with the dmm connected in series because it was faster to read the current value.
You can use series connected dmm that measures ac current or you can measure the ac voltage on the load resistor and compute the current value. As like for the other 2 resistors.
I used the dmm on 10A scale which added 0.3r in series with the load so there will be a small error.
I did it with the dmm connected in series because it was faster to read the current value.
