@brian92fs - all mosfets (vertical and lateral) have catching diodes built in (D2/D3). No need to add them here
Indeed: short and simple description, https://toshiba.semicon-storage.com...cs-of-mosfetsbody-diode-idr-idrp-vdsf-tr.html
The slow start mechanism is quite interesting, it could potentially make the amplifier more stable and listenable in stressful situations, what are the audible differences between this one and the stock
It’s not a slow start. It’s a bootstrap that raises the input impedance to around 10k to 13k. This allows for smaller feedback resistor for lower noise while maintaining a reasonably high input impedance.
The problem is the input CR filter still sees the 2.2k ground resistor, causing the input cap to be very large. Around 47u which makes only electrolytic caps reasonable.
The problem is the input CR filter still sees the 2.2k ground resistor, causing the input cap to be very large. Around 47u which makes only electrolytic caps reasonable.
Douglas selfs designs are often geared toward commercial manufacturers where numbers on a data sheet are a selling point. If your product has a lower noise stat, maybe it sells better than the competition
Yes that will also happen, but the dominant characteristic here is the slow start
Adding on above the said high impedance is also nomadic in nature and could be between 1k and 5k at any point in time thus further making the high impedance effect a non dominant characteristic
I am confused.
What TMC should we use ....
What you say brian?
I want to completly remove the cap 5pF acros the feedback resistor.
It seems I could.
I still want to use the 2 diodes CCS.
Maybe use 2 separate for IPS and VAS ..,
Is adding BAV21 clamp for the VAS transistor going to hellp in any way?
What TMC should we use ....
What you say brian?
I want to completly remove the cap 5pF acros the feedback resistor.
It seems I could.
I still want to use the 2 diodes CCS.
Maybe use 2 separate for IPS and VAS ..,
Is adding BAV21 clamp for the VAS transistor going to hellp in any way?
Thanks @gary s
It is just that I am listening to all different suggestions from all guys.
I have to decide what advices are good.
There are so many ways to change.
I think I will get a headache from all advices.
Best if I decide on my own. And make a final decision 🙂
The amplifier is surely improved since the first version.
Maybe time to say it is enough now .... say this case is closed!
It is just that I am listening to all different suggestions from all guys.
I have to decide what advices are good.
There are so many ways to change.
I think I will get a headache from all advices.
Best if I decide on my own. And make a final decision 🙂
The amplifier is surely improved since the first version.
Maybe time to say it is enough now .... say this case is closed!
Yep - lots of advice. Can get overwhelming.
For the CCS, using two diode strings increases complexity but improves slew rate. And possibly recovery under hard clipping.
For the TMC, you have to run a loop gain analysis. But generally speaking a 1 to 4 or 1 to 5 ratio between C5 and C3 is good.
I’m traveling today. But I can run a loop gain analysis tomorrow.
For the CCS, using two diode strings increases complexity but improves slew rate. And possibly recovery under hard clipping.
For the TMC, you have to run a loop gain analysis. But generally speaking a 1 to 4 or 1 to 5 ratio between C5 and C3 is good.
I’m traveling today. But I can run a loop gain analysis tomorrow.
Why is that? You can answer the questions after you return from your travel.
If anyone else knows the reason, please let me know.
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Bob Cordell discusses it in his book. He indicates that making the second cap larger is suggested, but does not explicitly state how big. I arrive at the 1-4 / 1-5 ratios from empirical evidence from the numerous designs on this site... done by people a lot smarter and more experienced than me 🙂
I strongly advice against it.
You shouldn't do this unless you simulate OLG and confirm stability of the amp (phase and gain margins).
Changing these values without simulating OLG is like shooting in the dark...
Value (or presence) of C7 explicitly depends on OLG simulation, not on the Thd results.
Also from my experience, usually when you sim for lowest Thd, stability of the amp suffers.
These 2 things rarely go together, usually they go in opposite directions.
Bottom line - you can't design good amp without simulating OLG (phase/gain margins) and aiming exclusively for lowest Thd.
Well, my business travel got canceled at the last minute
I agree with minek123. It would help a lot to learn how to perform a loop gain analysis. It's really a requirement if you want to design something that is stable
With that said, I ran it on your design and got 17db and 49 degrees. Technically stable, but a bit more safety margin would be good. Adding back C7 with a value of 2.2p gets it to 28db and 61 degrees - that seems a lot safer to me and the value for C7 seems reasonable.
Also, I looked at the single vs split CCS using diode strings. Slew rate symmetry improves a tiny bit with split CCSs but not enough to warrant the added complexity. It might matter more with higher rail voltages, but not for 20V rails. Clipping recovery looks good as well.
Other suggestions - this doesn't matter for the simulation phase, but for the actual PCBs, I'd suggest adding 1R drain resistors to the output that can be bypassed with jumpers. The jumpers would be removed to allow the bias to be measured and adjusted, then reinstalled for actual use. The other option is to have the builders use a power supply with a CRC filter and measure the bias across the R.
I agree with minek123. It would help a lot to learn how to perform a loop gain analysis. It's really a requirement if you want to design something that is stable
With that said, I ran it on your design and got 17db and 49 degrees. Technically stable, but a bit more safety margin would be good. Adding back C7 with a value of 2.2p gets it to 28db and 61 degrees - that seems a lot safer to me and the value for C7 seems reasonable.
Also, I looked at the single vs split CCS using diode strings. Slew rate symmetry improves a tiny bit with split CCSs but not enough to warrant the added complexity. It might matter more with higher rail voltages, but not for 20V rails. Clipping recovery looks good as well.
Other suggestions - this doesn't matter for the simulation phase, but for the actual PCBs, I'd suggest adding 1R drain resistors to the output that can be bypassed with jumpers. The jumpers would be removed to allow the bias to be measured and adjusted, then reinstalled for actual use. The other option is to have the builders use a power supply with a CRC filter and measure the bias across the R.
For a build of this, it looks like the output devices will put out 5W of dissipation worst case. This would mean it could work with a small mini-Disspante 200m deep 2U chassis and still run cool. Avel Lindberg 50VA transformers are 76mm in diameter. You might be able to fit a dual mono build into this chassis using these transformers.
Alternatively, dissipation is about 20W per device at 1A of bias - if someone wanted to try Class A. This should work in a mini-Disspante 250m deep 2U chassis with the heatsinks running between 50C and 60C.
Alternatively, dissipation is about 20W per device at 1A of bias - if someone wanted to try Class A. This should work in a mini-Disspante 250m deep 2U chassis with the heatsinks running between 50C and 60C.
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Lineup - a couple of considerations to fine tune things:
- For feedback cap C1, I'd suggest a bipolar cap. When you look at available values, 100uF is much easier to source than 68u.
- For C16, I suspect 10u is probably enough. When I've done PSRR tests, you don't get much past 10u and very little past 47u.
- For the bias bypass cap C9, 100n to 220n is probably enough and you can use a poly film cap. through the larger 1u electro probably doesn't do any harm.
- For the IPS CCS, I'd suggest dropping R2 to 47 and adding a 100R pot to allow the current to be trimmed. You can add a 1K resistor to the collector of U5 to allow the current to be measured and set.
- I mentioned earlier adding 1R drain resistors with bypass jumpers to allow the builder to measure and adjust the OPS bias.
- For the R25 ground lift resistor, adding a 100n bypass cap would be nice.
- Consider adding protection diodes to ground on each rail. This prevents the rails from reversing polarity under a fault , such as the failure of one of the rails
- Consider 100n bypass caps for the 4 electros C10, C11, C14 and C15. For C14 and C15 the 100n cap goes before the resistor.
#259 Ultima Thule
#189 bucks bunny
#190 wahab
I am sorry that their advice and arguments are not understood at all.
This worst case scenario is
When the output is saturated at the negative rail, the current flowing through U6 is zero, so U7 becomes just a base-emitter diode.
Therefore, R3 + its diode steals most of the current flowing to the reference voltage D3 + D2.
As a result, the reference voltage drops, and the current flowing through the IPS also sharply decreases.
When IPS turns off, all positive side transistors U3, U4, U11, U10, and U11 also turn off, causing latch-up with the output stuck to the negative side.
Lineup, your latest schematics seem to approximate the worst case scenario.
brian,
Rather than relying on the results of spice or the circuits of famous designers, we recommend that you get into the habit of thinking about ``why things are the way they are.''
If you do that, I think you'll come up with the idea, ``Let's check the U5 current to see what happens to the IPS tail current when the output clips.''
In this way, simulation will become a more useful tool.
Furthermore, "U7 should generate heat, so what will happen if that happens?"
When Q7 is 75℃
(The dotted line is the original room temperature value)
(The dotted line is the original room temperature value)
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Methink that Self is half right in this one, it s not exactly the transistor that improve the SR, yes and no, put the resistance in serial with the VAS base and add a 100nF cap from base of VAS to negative rail, you ll get the same result as what you measured with the active device implemented in the VAS side.