I present to you: The ortogonal power-signal 3D architecture (TOPS3D)
Run all power feed only in z/x plane and all signal only in y plane. I.e requires two boards, on e on top of the other separated by say 2 inch / 5 cm.
Signal connectors on top of any box. Power on back as usual.
Any component with signal must have component on bottom side so that a vertical pin (or coax) can connect to the (top) signal reception/distribution board. Impedance correctness everywhere of course.
You read it here first ;-)
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Run all power feed only in z/x plane and all signal only in y plane. I.e requires two boards, on e on top of the other separated by say 2 inch / 5 cm.
Signal connectors on top of any box. Power on back as usual.
Any component with signal must have component on bottom side so that a vertical pin (or coax) can connect to the (top) signal reception/distribution board. Impedance correctness everywhere of course.
You read it here first ;-)
//
Hey TNT, I already have decided to use a 4-layer PCB with S-GND-GND-S stackup, dielectric and layer height will be decided by the manufacturer's capabilities, probably 1.6mm. I used Aisler before and from what I can see it is in spec with the BGA MCU, this component will be the limiting factor PCB production.
I`m not experienced enough to decide if orthogonal routing might be an option but according to this blog post, it is usually not recommended.
https://resources.altium.com/p/case-against-orthogonal-trace-routing-multilayer-pcbs
I`m not experienced enough to decide if orthogonal routing might be an option but according to this blog post, it is usually not recommended.
https://resources.altium.com/p/case-against-orthogonal-trace-routing-multilayer-pcbs
We haven't talked about clock edge rates so far. Did mention a Tiny VNA and some probes that can be used to look at some of the very high frequency RF hash associated with fast edge rates.
Haven't talked much about stackup either. I would probably make layer 2 ground, and layer 3 mostly a large are of fill with +5v pre-regulated power on it on it. Layers 1 and 4 would for signals and extra ground fill. Don't see why two adjacent layers of ground are probably needed. There would be some coupling between them anyway so its not necessarily so easy to make one a dirty ground and the other a clean ground. Seems to me its more important to lay out the board so that noisy ground return currents don't tend to flow in the same area where clean circuity needs to work. My two cents anyway.
Haven't talked much about stackup either. I would probably make layer 2 ground, and layer 3 mostly a large are of fill with +5v pre-regulated power on it on it. Layers 1 and 4 would for signals and extra ground fill. Don't see why two adjacent layers of ground are probably needed. There would be some coupling between them anyway so its not necessarily so easy to make one a dirty ground and the other a clean ground. Seems to me its more important to lay out the board so that noisy ground return currents don't tend to flow in the same area where clean circuity needs to work. My two cents anyway.
4 Layer S - GND - GND S is very common, why should I use something exotic?
Every post and tutorial for signal integrity I have read so far, generally recommends a stackup with 2 inner GND layers. And I see there are good reasons for it, most importantly the current return path. Having GND-PWR-SIG is in my opinion not advantageous.
Whats a Tiny VNA?
Every post and tutorial for signal integrity I have read so far, generally recommends a stackup with 2 inner GND layers. And I see there are good reasons for it, most importantly the current return path. Having GND-PWR-SIG is in my opinion not advantageous.
Whats a Tiny VNA?
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Nothing exotic. Just think first, design board second. Not the other way around....why should I use something exotic?
Maybe study the thread at: https://www.diyaudio.com/community/...decoupling-capacitor-simulation-model.382329/ ... to help get you started
One point I would like to make about what you seem to have been reading is that its about high speed digital. DACs are mixed signal, and most of them are not running at several hundred MHz and or at GHz. Some clock edge noise might be up there though. DACs are partly digital, partly analog RF, and partly low noise, low distortion audio frequency circuitry. Its not the same thing as a board mostly full of high speed digital.
EDIT:
Some resources...
https://www.analog.com/media/en/training-seminars/tutorials/MT-031.pdf
https://www.analog.com/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter12.pdf ...including the section on "Design PCBs Thoughtfully
https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3660.html
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Nothing wrong with thinking first, the problem I see with relying on implementation discussed in threads is that they are more complicated to read and understand. The question is not why I use something that might be a good choice. There are good tutorials and blog posts (in that case altium) I can rely on, that offer a solid and well-tested starting point for my implementation.Nothing exotic. Just think first, design board second. Not the other way around.
Maybe study the thread at: https://www.diyaudio.com/community/...decoupling-capacitor-simulation-model.382329/ ... to help get you started
One point I would like to make about what to seem to have been reading is that its about high speed digital. DACs are mixed signal, and most of them are not running at several hundred MHz and or at GHz. Some clock edge noise might be up there though. DACs are partly digital, partly analog RF, and partly low noise, low distortion audio frequency circuitry. Its not the same thing as a board mostly full of high speed digital.
Sorry if I missed your link, the thread was moving quite fast sometimes. What are you referring to?
Did you read the following: https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3491.html...that offer a solid and well-tested starting point for my implementation.
I can see why vertical routing within one and the same bord is perhaps not a good thing but I ment between boards 😉Hey TNT, I already have decided to use a 4-layer PCB with S-GND-GND-S stackup, dielectric and layer height will be decided by the manufacturer's capabilities, probably 1.6mm. I used Aisler before and from what I can see it is in spec with the BGA MCU, this component will be the limiting factor PCB production.
I`m not experienced enough to decide if orthogonal routing might be an option but according to this blog post, it is usually not recommended.
https://resources.altium.com/p/case-against-orthogonal-trace-routing-multilayer-pcbs
//
Vertical routing has already found its way into some high-end dacs 🤣
https://www.diyaudio.com/community/...ctusb_boardtodac_withtwistedpairs-jpg.976911/
https://www.diyaudio.com/community/...ctusb_boardtodac_withtwistedpairs-jpg.976911/
that's all very reasonable, and is indeed what I try to accomplish. But ty for the linkDid you read the following: https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3491.html
EDIT: regarding stackup
For the area of the DAC, layer 4 can be mostly filled with PWR, The whole routing can be done on one side, and addidional ground fences could be used to devide digital from analog signals
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Note that the Maxim app-note is for an ADC targeted at IF sampling applications (>1MHz). Some of the suggestions are not that relevant for an audio DAC. IME ground fences or other extraordinary layout schemes are not needed for reaching datasheet level performance and good sound.
So what would be your suggestion, having [SNG - GND - GND - PWR] or rather [Analog SNG - GND - GND - Digital SNG] with PWR tracesNote that the Maxim app-note is for an ADC targeted at IF sampling applications (>1MHz). Some of the suggestions are not that relevant for an audio DAC. IME ground fences or other extraordinary layout schemes are not needed for reaching datasheet level performance and good sound.
It is probably possible to reach good performance with various 4-layer stackups. I normally use SGN-GND-PWR-GND stackup. Here is one result using such board.
BTW the measurement was made with a separate USB-I2S board having digital isolators for dac signals. If you put MCU on the same board with DAC without digital isolators then some extraordinary layout schemes may be needed.
BTW the measurement was made with a separate USB-I2S board having digital isolators for dac signals. If you put MCU on the same board with DAC without digital isolators then some extraordinary layout schemes may be needed.
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and regarding fast startup, I'm not quite sure if I understood the fast start-up implementation correctly,
I assume that fast start-up is done via the typical application below, but I'm a bit confused.
Best
I assume that fast start-up is done via the typical application below, but I'm a bit confused.
Best
For me at least, it isn't whether analog signals are on one outside layer of the PCB and digital signals are on the other outside layer. Maybe think about layout instead more in terms of signal flow. Traditionally, hand drawn schematics would often show signal flow from from input to output visually depicted as being from left to right on the schematic. Voltage rails were shown top and bottom with bias currents flowing downhill from positive to negative. To summarize then, signal flow from left to right, power flow from top to bottom.So what would be your suggestion, having [SNG - GND - GND - PWR] or rather [Analog SNG - GND - GND - Digital SNG] with PWR traces
You may find it helpful to consider dac layout in a similar way. Digital signals go in on the left, analog audio signals exit on the right. Digital and analog signals can be kept physically separated in that same way to a large extent. However sometimes it may be necessary to go to another layer with one type of signal or the other, but it usually doesn't have to stay at that other layer for much distance.
The difference between planes (ground and or power) and fill areas is that the design rules tend to be more strictly defined for planes. Its possible to make a fill area exactly like a plane, but its up to the designer to exercise discipline if the design rules don't force the fill area to strictly comply as a plane to in that case. Thus, fill areas can be more adaptable so long as layout choices are made thoughtfully. For that reason I might make layer 2 a ground plane, layer 3 power fill, and layer 4 into areas of ground fill but with maybe with some carefully considered trace routing if needed.
Again, its important to start to think in terms of where currents flow in a ground plane as a function of frequency and or in terms of rise-time verses elapsed time since the last switching edge (in other words, in terms of the frequency domain view and or in terms of the time domain view). Keep noisy ground currents from flowing in areas carrying sensitive analog signals. Most of that can be done with thoughtful layout. Its also important to think in terms of signal flow and to keep that flow logically organized to minimize unwanted stray coupling between signals that might otherwise harmfully interfere with each other. Hopefully that makes sense.
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