This red underlined is...hmmm...say not "clear". It is not without logic DD mismatch some things only... 🙁
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BCK, Bit Clock, and SCK, System Clock = are the different names for the SAME signal line.
ONE BCK or SCK period is = ONE Bit of DATA
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MCK Master clock = typically higher F than BCK/SCK and it is 22.xxx MHz / 24.xxx MHz contemporary interfaces.
that is is for 512 X Fs. In some devices MCKs are 2 x 512 = 1024 x Fs
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Depending on Fs base 44.1KHz and 48KHz, we have tipicaly 2 MCK (2 oscilators) on the boards. 22.xxxMHz / 24.xxx MHz
From THIS Master Clock ALL other line are derived and this is the main use
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Also the LE line is marked differently but have the same function (to start conversion) = LE (Latch Enable), LRlatch, WS (word Select)
DATA could be marked as SD (serial Data), DATAL, DATAR
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Ing. Doede Douma achieved this experimentally and not by theory and logic from Data sheet . Although since he is an engineer, he also knows the theory. But the average reader will not understand anything if we bury him with so many technicalities.
This is still a hack and everyone does this at their own risk for each particular chip.
Happy hacking.😀
This is still a hack and everyone does this at their own risk for each particular chip.
Happy hacking.😀
dont calculate too much, when you got that feeling "i mean shaking head....", thats it.
now i stick ad1865 and pcm63, pcm63 burn around 500hrs, sound beautiful.
Not true. SCK (Serial clock) is I2S bit clock whereas System Clock is used internally by the DAC chip e.g. for filters and modulators. They may need to be synchronized but they are not the same signal.
What may be misleading is that some older DAC chips (such as PCM1794) use SCK abbreviation for System Clock.
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Not sure about the AD, but MP7614 (or MP7616 16-bits) from EXAR is true R-2R based on your requirements 😉 ... also chips like DAC702 ...
LE is NOT LRCLK and is NOT WS. LE has a variable mark:space ratio while LRCKL/LRLATCH is pretty much always 50:50. WS is strictly a Philips/NXP thing and is the inverse of LRCLK.
Hi, Zoran,
I must confess that I'm not certain of what you are suggesting. I'm uncertain of whether we agree, or not. Perhaps, some additional information regarding what I'm suggesting will help make that more clear.
The digital audio data stream (I2S, EIAJ, etc.) input to the DAC chip is serial, with left and right channel data for each sample being time-multiplexed on the stream. As a result, Inter-channel data for each sample is inherently presented with constant time-delay that's inversely proportional to the sample rate. Yes, this is a frequency dependent phase-shift, but it's linear, resulting in a simple time-delay. The delay will manifest at the analog signal output of the DAC if not corrected prior to conversion. DAC chips featuring an internal digital interpolation-filter unit all feature the necessary delay correction within the filter unit. Older DAC chips, without an internal digital filter (i.e., AD1865, AD1862, PCM1704), don't provide such inter-channel delay correction.
My view is that, externally correcting for the microsecond inter-channel delay isn't worth the trouble and the potential ground noise impact, of the ****-register chips which are typically utilized to do so. I hope that helps clarify what I'm suggesting, and why. Just my opinion.
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By inherent delay, I mean, the data as sent to the DAC chip in a time-multiplexed signal.
What do you mean?
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The AD1862's are mono devices and as such any delay incurred is down to the end user and the choice of how to operate them. On the subject of delay, the dacs are innocent.
I’ve not suggested that there is guilt anywhere in the DAC. Just that the DIY bother of externally time-aligning the channels via glue logic is essentially nullified in practice.
I imagine that, for some, whatever their reasons may be, the bother is the point of the exercise. The only reason I would need to correct what I perceive, and I do mean perceive as I have no intention seeking a conclusion one way or the other, as an error is that it is there.
Yes, I suspected as much. So, what’s to be gained in speaker listening reality from zero’ing a uS inter-channel delay? Nothing. I guarantee that your speakers are located somewhere outside of being equidistant from each ear by more than 0.15 inches. You‘d have to re-verify the range each time you sat down to listen. Chances are very likely that your ears alone are asymmetrically located on your head by a difference of greater than 0.15 in. Plus, there’s no way that your head remiains absolutely fixed to less than 0.15 inches of movement while listening to speakers. None.
What’s to be sacrificed, aside from the mounting of several additional SMD chip packages, plus the incremental cost of those parts and their associated PCB area, perhaps nothing consequential. However, there is the possibility that the increased ground noise on the PCB generated by the additional logic chips running at over 2.8 MHz each could adversely affect conversion clock jitter. I don’t have measured jitter data to quantify that conclusively, but the circuit mechanisms certainly exists.
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I don't consider 2.8Mhz to be particularly fast and the additional chip count is a grand total of one. But it is all moot anyway. I have little interest in NOS and the JLSounds USB I/F provides simultaneous data anyway.
Yes but I just want to point that the main function is the same. to tell DAC to convet datas. The formats are different but every line still has the same purpose. (inversion of LRCK is just about when the conversion starts from the rising or falling edge. Also -BCK is.
For the example comapre PHI time simoultaneous format and this AD/BB formats.
Yes with I2S and other formats with booth L and R channel DATA in same serial line. But in other data formats also serial type the L and R channels are divided into separate lines and feed simultaneously
Non-oversampling Digital filter-less DAC Concept by Ryohei Kusunoki Nov. 1996
https://archive.is/92aQ5