Andrea, you are constantly confounding FIFO buffer issues and the SI parts intrinsic jitter.
I am sure that the setup has a problem because of the differences the incloming clock makes.
The jury is still out however regarding the adequance of the SI part for its intentend purpose in the DAM1021.
I am sure that the setup has a problem because of the differences the incloming clock makes.
The jury is still out however regarding the adequance of the SI part for its intentend purpose in the DAM1021.
Theoretically it's true, but why when replacing the source the DAC sounds different?
Keep in mind that Ian uses plenty of SRAM in his FIFO, I believe 4Mbit, but anyway replacing the source affects the output.
There are many interference inside the FPGA and even inside the PCB.
Only optical isolation performs as a brickwall between input and the output.
Well, if Soeren would make it possible to clock the DAM1021 independently from the incoming S/PDIF signal (which I understand is theoretically possible) you could put a great clock in the box with the converters and have them all in sync. With a single DAM1021 you could just use the SI part as the master and use an S/PDIF output to clock the source.
Yes it sound different. But not due to added jitter/PN from the source but from wander, triggering frequency changes of the Si.
Ian seem to have other problems and most probably isolation - yes.
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Ian seem to have other problems and most probably isolation - yes.
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With our new FIFO Lite you can sync a pair of DAC, we provide double output (MCLK, DR, DL, LRCK).
Of course, regardless of the source.
You still have to handle the difference in clock frequencys... how?
Its theoretically possible via a fifo buffer :-D
Or send the DAC clock back to the source - but thats "special"...
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More than one clock is never easy. Good designers in the 80s synced the switching supplie's clock with the converter clock to prevent issues.
Maybe metal shielding inside the box is necessary. I am currently building a 32 channel DAC with 16 DAM1021 PCBs. Haven't tried it yet... 😀
Yes, but the DAM1021 is not configured to accept a different incoming clock than the one from the source.
Sorry, but it's not so.
The problems come either from the SI and from the FIFO architecture.
And the SI514 (not the SI570, a little better but always a poor oscillator) are designed for telecommunication, the manufacturer has clearly specified the purpose in the datasheet, and also the jitter measurements are suitable for telecommunication, since the integration bandwidth used for the jitter measurement was 12 kHz to 20 MHz!!!!!
I cant see how you are not technically persuaded that jitter/pn cant get thru a 44 (or more) sample RAM. Thats really stubborn 🙂 again - given my def.
But hey - clock quality is also stability ("ppm") and that can make a difference in some designs - like here 🙂
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But hey - clock quality is also stability ("ppm") and that can make a difference in some designs - like here 🙂
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Well, so far nobody has heard the DAM1021 with the FIFO out of the way and maybe without possible interference between the incoming and on-board generated clock. It might actually be sufficient, we just don't know.
In some sense some have. The new models with inbuilt USB function will not adjust the Si clock. My buddy who owns one prefers USB as source.
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No, actually it's not possible, he should redesign all the front end of the DAM.
You can do the job with a FIFO as the master clock for all the DACs, but not with the DAM1021.
Not a practical way and no market since the available sources usually don't accept the clock back.