So it's a source of THD from the R2R architecture that we can do nothing about? But of course if Vref impedance is 0 then current draw doesn't matter.
It would be so exciting if Vref circuitry doesn't matter and we get to claim perfection on the dam dacs. But on the other hand, if it does make a difference, it would be an opportunity for us to break new grounds in our understanding of psychoacoustics, and perhaps be one step closer to understanding the R2R/DS mystery.
It would be so exciting if Vref circuitry doesn't matter and we get to claim perfection on the dam dacs. But on the other hand, if it does make a difference, it would be an opportunity for us to break new grounds in our understanding of psychoacoustics, and perhaps be one step closer to understanding the R2R/DS mystery.
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It could be addressed in the digital domain in the same way as the resistor imperfections. If it is worth doing so is the other question.
You can definitely hear the difference in ABX, but it’s probably a slight shift in localization than anything else. I really hope Soren can take a little time to enable the sync function and fix the delay problem which as we’re starting to see is non-negligible in some tests.
I've pondered sending the clock output lines off to the 2nd board just to see how the 2nd board would react by only one board having control of the clock generator. If the boards boot in an identical state and receive the same clock.... crude as $^%$^& but what the heck.
Sören, do you delay one channel (one and same board) to compensate for the serial fashion of PCM?
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I was wondering that myself, the delay should theoretically should only be the difference in the clock generator phase if there is an exact constant that the code is referencing to maintain an exact fifo buffer length so no 2 boards would be different if fed the same signal. When Soren says they track to x amount of one another, he doesn't elaborate on how the lock is maintained and if there is a target buffer length to maintain once lock is obtained and synced. The clock from a good usb-i2s converter should be sufficient to keep both boards in near perfect sync without worrying about randomized delay on a per lock basis.
EDIT: Reposted for clarity.
EDIT: Reposted for clarity.
@soekris
I am delighted that Soekris is exhibitor at HIGH END 2019 in Munich.
Is it possible to listen to all of your three audiophile DACs (1321, 1421, 1541)?
Thanks
Matt
I am delighted that Soekris is exhibitor at HIGH END 2019 in Munich.
Is it possible to listen to all of your three audiophile DACs (1321, 1421, 1541)?
Thanks
Matt
I did not measure ripple yet. I understood from hifiduino site that remaining ripple is 1 mV. But this may already be different for recent revisions...
Fedde
Fedde
I have bought dam1021 v5 very recently. Should I implement the vref mod. I don't have any experience on this. As I have gone through various posts, I found that e 12 pieces of 1000uf 16v capacitor can be used for vref mod. I have 1000 uf 16v capacitor (ESR 7), can I use those? Is it all that I should do for vref mod. Need your kind suggestions.
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Those seem to be fine caps. Put them on and you should hear a big difference. But before you do that, if you can record the outputs and post them, many people including me will be very grateful.
Soren, if you use the shift register buffer, maybe you should get rid of the opamp Voltage regulator too. I think TotalDAC might be using shunt supplies in new versions which is why there’s no caps - there is no need since good shunt supply such as UltraBiB have extremely low impedance over all frequency. Maybe in 5 years 😉
Your picture revealed that Soren improved the vref circuit on rev5 to match his commercial products. They dont have the load resistors any more. Can someone with an actual background in electrical engineering explain what benefits it might have? And whether it’s possible to mod on earlier revisions? 🙂
Gosh I feel like if I ever need a second DAC, I might want to just get the TotalDAC... the price is a bit steeper than it needs to be though...
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Yes, add them through the vias,
for the leads that go through the vias: don't cut them short, so you can use those leads to add some additional caps on the backside.
Also add a cap for the clock, you can also use the available vias, see this post.
OT
I'm just using my 1021 for playing music, a lot of music 😀
Thanks Søren, I think it's a great product.
I'm just using my 1021 for playing music, a lot of music 😀
Thanks Søren, I think it's a great product.
Thanks for the suggestion, is it the place where I should put a cap for clock? Can you please give me some more detail, what cap should I use, volt, mfd and orientation.
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Why would you want to add a cap, I assume to the clock? There’s really no point. Clock jitter is <1ps, fpga jitter is hundreds of times that.
Source: The Soekris R-2R DAC: Technical Details | H i F i D U I N O
It is a pretty hefty regulator. And it seems the only 3.3v regulator on the board. It must also supply 3.3V to:
3.3V need of the FPGA
Clean side of signal isolators
SPDIF LVDS receivers
Microprocessor
Flash memory
Other components (like the shift registers?)
Good thing it is implemented next to the clock of all places.
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Doesn't supply shift registers (I think). I don't see why the others matter. Clocking is already very good. Try if you have the cap though seems to be an easy and harmless mod. Do report on ABX results if you have recording equipment... might be a new discovery
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