Hi,
Real world THD+N measurement on a symetrical design with mosfet output.
100W and 30W 8Ohm BW=80kHz
100W first then 30W
\\\Jens
Real world THD+N measurement on a symetrical design with mosfet output.
100W and 30W 8Ohm BW=80kHz
100W first then 30W
\\\Jens
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If you get weird results or pages or threads don't display then clear your browser cache of all history and also delete all temp files (a disk clean)
I don't think is only that. Why still4given vent to correct page, and for me it shows correct page?
No. The RB-1090 has a cascoded input stage, and a cascoded VAS, the RB-1080 does not. I don't call that identical.
Like I said, elektrotanya.com has the RB-1080 service manual.
I have never yet had any troubles with the EF transistor blowing if the main VAS transistor is current-limited in the usual way. What would make it blow if it is only turned on enough to allow, say, 20 mA, through the main VAS transistor?
I don't see the failure mechanism.
The link takes me straight to #207.
From the relatively low THD levels, I assume there are EF's applied to the VAS's?
Can you show us the schematic?
Yes, the VAS is buffered, and no - I cannot share the schematics - sorry ...
It's fairly standard stuff:
Input is cascoded BJT - interface to VAS is not seen often - no current mirrors
VAS is cascoded and buffered to isolate the non linear loading output stage.
Output stage for the plots are Source followers
Components are all SMT except for output devices
Circuit is not at all optimized regarding loop (Purely done on the simulator) and DC currents in the different stages, i expect to lower THD by a factor of 2-3 at higher frequencies by doing this.
Best regards
Jens
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I didn't call it Class-S, Sandman did.
+10 dB is ten times the power. Isn't that asking rather a lot?
I suppose Class-G might be able to do it.
I meant, is there an EF inside the VAS Miller loop?
I wasn't thinking of buffering the VAS output.
I don't have real data - only simulated - but time domain has been stable until now.
Gain reserve in the simulator is about 42dB at 20kHz and phase margin > 50 degrees - this was done so I did not have to deal with destructive oscillations.
I need to build a second prototype and optimize the open loop response before I will go into details on loop.
The rest of the circuit is still early days - I just posted in relation to discussion about balanced topologies.
Best regards
Jens
Simulation shows (did you take look to the simulation attached?) that VAS current limiter does not start to limit and EF transistor goes up over 2 W of dissipation. Did you tray to simulate it, no need to blow real transistor? When I made my first blameless after your article series of power amp distortions in WW, it blew the EF transistor (there was not VAS current-limited yet, but I think that it could not save it) after some hard clipping transients, and then I included that protection resistor and it never happened again even with no current limiter.
By the way with your 10R resistor in the VAS emitter, current limit is set a bit over 60 mA.
I attached again the simulation plot, with output voltage, EF transistor (Q7) current and VAS (Q9) current.
BR Damir
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When you were 6 years, ICEpowers founder Karsten worked on his Phd... I was an apprentice back then (Still is for that matter) I guess the main point of technical and commercial focus since has been switched amplifier technology.
\\\Jens
Something wrong with your simulation, I think.
Well, surely there's your problem. No current-limiting.
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