CFA Topology Audio Amplifiers

Ill try to add this latest mirror to the others one evening this week - going to be a busy one as I am on the road again.
BTW I wouldn't bother with the JFET/DMOS one shown as part of the inverting current conveyor. To some extent it was a stunt, to see how something like it could be made to work, play with floating bias sources that have essentially no d.c. drain, and to cater to the partisans of FETs. And as mentioned, the JFETs, at least, need to be matched, although with a slight reduction in speed the LSK389 pair could be used. It's also very voltage-hungry.

What might be fun though is a CFA front end with JFETs, and maybe a local loop to stabilize and reduce input resistance. Or even local stabilization for the traditional bipolar gm front end.
 
I am getting stability issues on the Boxall - before I go slapping R's and C's around this thing, any insights - I am not at all familiar with this topology.
On a separate note, I cascoded a Wilson and got to 50ppm (20kHz)

I've come up with a way to raise front diamond gm (some wont like it, but it works and especially so for a discrete amp where matching is an issue for DC stability with low value degenaration resistors in the diamond front end) and with the cascoded Wilson, we are down to 30ppm at 20 kHz. LTspice file attached.

Plots of loop gain also attached

View attachment fx-Amp_advanced_3.asc
 

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I am getting stability issues on the Boxall - before I go slapping R's and C's around this thing, any insights - I am not at all familiar with this topology.
On a separate note, I cascoded a Wilson and got to 50ppm (20kHz)

I've come up with a way to raise front diamond gm (some wont like it, but it works and especially so for a discrete amp where matching is an issue for DC stability with low value degenaration resistors in the diamond front end) and with the cascoded Wilson, we are down to 30ppm at 20 kHz. LTspice file attached.

Plots of loop gain also attached

View attachment 370141

I see now you are going the same path I was going when designed my GainWire pre amp. It's easy to get very low distortion with current conveyour, the problem is to find OPS with benign input impedance, otherwise it will destroy all low distortion of the current conveyour.
BR Damir
 
Yes, agree with your point - the OPS input behaviour is critical. I experimented with this approach for a line amp stage a few years ago, but never carried it forward to a practical design. It works very well in that type of application and over a wide gain range - I used a simple 2 transistor mirror.

For a PA, I think you need to run the conveyor at a reasonable current (5-10mA) so that the OPS input current is only a small percentage. Might also be an idea to think about how to recirculate the OPS input current some way . . .
 
Yes, agree with your point - the OPS input behaviour is critical. I experimented with this approach for a line amp stage a few years ago, but never carried it forward to a practical design. It works very well in that type of application and over a wide gain range - I used a simple 2 transistor mirror.

For a PA, I think you need to run the conveyor at a reasonable current (5-10mA) so that the OPS input current is only a small percentage. Might also be an idea to think about how to recirculate the OPS input current some way . . .

It's not only OPS input impedance but non linear input capacitance that matter, I think.
 
It's not only OPS input impedance but non linear input capacitance that matter, I think.
The bootstrapping of the input devices helps a lot, as the schematic shows (Q23, Q24). It will often result in a negative input impedance at some frequencies, but usually there is enough other C around which is not variable.

This is one of those situations where things that can be ignored normally can become important, like poor dielectric behavior of PCBs, so-called "hook". The effects are very process-dependent, and when I've mentioned them I often get assurances that this is irrelevant because it just doesn't happen anymore. My attitude is, anything that can happen associated with process variations sooner or later will.
 
Here for the sake of formality is a higher-voltage modified mirror design in a push-pull configuration, and using a little more current for the auxiliary Boxall transistors. Flat response when loaded with 100k needs a tiny capacitance, but the response in actual use will be determined by the capacitive loading of the following stage. With that 100k test load and swinging 16V p-p, by itself the predicted distortion is unbelievably low. I'll get round to looking at IMD soon. Power supply rejection should be very good but could be improved by bootstrapped cascoding of the e-follower parts, or even just a fine-tuned large impedance from each 10k to ground. It will also be affected strongly by the output impedance of the preceding stage.

Castor-Perry points out that the assumption, considering PSR, that the rails move in equal magnitudes and opposite directions is often not warranted, which is a good observation I think. If they did the symmetry of these circuits would help us.
 

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    Push-pull mirrors 09-09-13 001.jpg
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Here for the sake of formality is a higher-voltage modified mirror design in a push-pull configuration, and using a little more current for the auxiliary Boxall transistors. Flat response when loaded with 100k needs a tiny capacitance, but the response in actual use will be determined by the capacitive loading of the following stage. With that 100k test load and swinging 16V p-p, by itself the predicted distortion is unbelievably low. I'll get round to looking at IMD soon. Power supply rejection should be very good but could be improved by bootstrapped cascoding of the e-follower parts, or even just a fine-tuned large impedance from each 10k to ground. It will also be affected strongly by the output impedance of the preceding stage.

Castor-Perry points out that the assumption, considering PSR, that the rails move in equal magnitudes and opposite directions is often not warranted, which is a good observation I think. If they did the symmetry of these circuits would help us.


Try reduce:

R5,R16 to 2K.

R7,R8,R15,R17 to 200R.

Insert 10R into emitter of Q13 and Q8 before the base of Q7 and Q12.

It should cure some of the peaking and improve overall phase margin.
 
Try reduce:

R5,R16 to 2K.

R7,R8,R15,R17 to 200R.

Insert 10R into emitter of Q13 and Q8 before the base of Q7 and Q12.

It should cure some of the peaking and improve overall phase margin.
Thanks for those suggestions. What will be crucial is the rest of the circuit into which this may be embedded, particularly the output buffer and output stage, but it is conceivable that better phase margin here would still be helpful.

The choice of emitter ballasting (R7,8,15,17) is a tradeoff with noise for the CFA application. Smaller will be faster to be sure, but noisier.