ZM: Thank you for responding.
Your underlined answer is right on the money. I did [this morning] the experiment of Figure 2 of OTLAmp5 [using a stereo bjt TCA, and a dual secondary step-down toroid power transformer], and got zilch or a silencer [your verbiage]. The simultaneous presence of out-of-phase signals at the joined power output nodes wasted each other. The presence of out of phase signals at the output of each TCA was confirmed by having each TCA drive an independent 4 Ohm resistive load [i.e. no joining of their output nodes]
By contrast, the simultaneous presence of in-phase signals at the output node were additive [in the load] as you expected in an earlier thread for paralleling TCAs.
Consequently, Figure 2 of OTLAmp5 is not related at all [operation wise] to that of the [unique] simplified F6 schematic.
I'll do the experiment of Figure 1 of OTLAmp5 by using the two channels of a Threshold S/150 voltage source amplifier [VSA] to confirm [or not] the bridging operation.
Best regards
The schematic of the underlined experiment worked. I confirmed first [ by using a signal generator to power the toroid] that R and L power outputs were out of phase. I then played music via an A/D/S 730 loudspeaker.
Consequently, Figure 1 is another tool to bridge power amplifiers.
taking it historically - it's first tool to bridge power amplifier
regarding your pdf - I confess - didn't looked first time carefully enough right side of fig.2 , so didn't realized that black boxes are paralleled ( meant they are bridged , as in fig.1 ) ; that's why I replied when replied , about silencer effect .
ZM: The underlined statement by Mr. Pass may effectively say the following: The bottom JFET in the simplified F6 schematic is a TCA; because its power output is derived at its drain port which has high impedance. By contrast, the upper JFET is a VSA [common drain]; but with a voltage gain which is made equal to that generated by the bottom JFET for the symmetry of the output signal.
So, I'll go back to Figure 2 of OTLAmp5 and simply replace the upper TCA with a VSA. Suppose also that I can manipulte the voltage gain of this VSA to equal that of TCA.
Will this revised Figure 2 now give a useful power output or zilch?
May I add to the above thread. The phase of the output signal due to only the upper JFET [mentally disconnect it from the drain pin of the bottom JFET; and keep the load] is in-phase with that of its indicated transformer winding. The phase of the output signal due only to the lower JFET is also in phase with that generated by the upper JFET [mentally disconnect the source pin of the upper JFET and keep the load] . The lower JFET [common source] inverts the signal phase as it appears on its secondary winding; which is already out of phase with the upper transformer winding. The bottom secondary winding and its JFET do a double signal inversion. So the output signals from both JFETs are actually in phase at the output node and thus additive to drive the common load.
The answer to my question above to Mr. Pass or ZM has a high probability of a yes.
The answer to my question above to Mr. Pass or ZM has a high probability of a yes.
may but also may not
look at it in simpler way - just imagine both Jfets as rheostats ;
feeding them with input signal , you will vary both rheostats in exactly same amount , but in opposite directions
that sort of behavior is conditio sine qua non for perfect symmetry , and that symmetry is fact here
I don't know for better explanation , even if there is one
so , there is no place for usual common drain vs. common source categorization , even if you can call them in that way , observing solely halves ref. to load
you can put cap from output , then connect other end of speaker either to + or - leg of PSU ........ or you can make Transnova ........ and each time amp will work in same way (even if PSRR will suffer in some cases ) and my head will implode trying to find a proper name for output stage (halves ) operation mode
Thank you ZM for your explanation. What time is it in Serbia anyway? Sleepless in Serbia? The grey cells are working full throttle at this time of night! I hope you rest up. Best regards.may but also may not
look at it in simpler way - just imagine both Jfets as rheostats ;
feeding them with input signal , you will vary both rheostats in exactly same amount , but in opposite directions
that sort of behavior is conditio sine qua non for perfect symmetry , and that symmetry is fact here
I don't know for better explanation , even if there is one
so , there is no place for usual common drain vs. common source categorization , even if you can call them in that way , observing solely halves ref. to load
you can put cap from output , then connect other end of speaker either to + or - leg of PSU ........ or you can make Transnova ........ and each time amp will work in same way (even if PSRR will suffer in some cases ) and my head will implode trying to find a proper name for output stage (halves ) operation mode
now is 22.37
just helping my brighter , better organized , much more responsible and - of course- better half to - heh , what are proper words - aha - grind and cook tomato for tomato juice and tomato sauce
even if summer is pretty dry , tomato in our garden is wakoo - sort of magic beans tomato
now I'm going to fire a fire ;biiiig pot
just helping my brighter , better organized , much more responsible and - of course- better half to - heh , what are proper words - aha - grind and cook tomato for tomato juice and tomato sauce
even if summer is pretty dry , tomato in our garden is wakoo - sort of magic beans tomato
now I'm going to fire a fire ;biiiig pot
SJEP120R100 fet gate current
Does anyone understand the gate to source current of SIC FETs such as the SJEP120R100 under bias conditions expected in the F6? I have never worked with these beasts before and do not know what to expect.
Does anyone understand the gate to source current of SIC FETs such as the SJEP120R100 under bias conditions expected in the F6? I have never worked with these beasts before and do not know what to expect.
search est mater studiorum
gate current is - freely interpreted - pretty much negligible
all you need is voltage source with proper output impedance .......
say that two tiny Toshiba Jfets paralleled are good enough in Papa's J2 , to drive SS gate
gate current is - freely interpreted - pretty much negligible
all you need is voltage source with proper output impedance .......
say that two tiny Toshiba Jfets paralleled are good enough in Papa's J2 , to drive SS gate
search est mater studiorum
gate current is - freely interpreted - pretty much negligible
all you need is voltage source with proper output impedance .......
say that two tiny Toshiba Jfets paralleled are good enough in Papa's J2 , to drive SS gate
It there enough DC gate current that you should not pass it thru the transformer secondary?
Please go to post #292. It shows the updated and simplified F6 schematic. In it, Mr. Pass readjusted the phase relationships of the secondary windings of the transformer. Go ahead and put a circle [for phase] at the output node. The phase of the signal at the output node is the same as the phase of the input signal at the upper secondary winding, and the same as the phase of the signal shown for the primary winding. I am confident that no one will challenge [you or me] that this is the correct phase and/or answer. At this point a "Eureka" light lit up my brain [and hopefully yours too]. The instantaneous and individual contribution of voltage at/to the output from the upper and the lower JFEts must always be in-phase [as declared above].
So, this is what I see as I look at the simplified F6 schematic. The upper JFET is a non-phase inverting voltage source amplifier [VSA]. It is connected in series with the bottom JFET which is a phase-inverting transconconductance amplifier [TCA]. These two amplifiers are independently controlled by the secondary windings; but they work together, and their individual contribution [of voltage and current to the load is [and must be] always in phase, and thus is additive rather than destructive.
Clearly, in good time, Mr. Pass will have the only and best explanation for the operation of his F6 creation.
@ lhquam
well - leakage currents are probably too small to worry about but , speaking of dynamic conditions , better to leave small signal xformer's secondaries to work strictly in AC domain
well - leakage currents are probably too small to worry about but , speaking of dynamic conditions , better to leave small signal xformer's secondaries to work strictly in AC domain
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