I am not sure why anyone would prefer to use 2 heatsinks with the V2 combo board. The 50 mm MOSFET spacing is too close. That spacing would be optimal spacing for a heatsink that is 100 mm wide.
Doesn't anyone want to implement the balanced-X configuration? I am not sure how P3 is incorporated into the balanced-X. Anyone with a suggestion?
UKToecutter:
Your layouts keep getting better. Good work.
My only concern now is the proximity of the JFETs to the output signal and to the feedback resistors R7-R10. My concern feedback resistors is that their temperature changes dramatically with the output level, and there is likely to be significant thermal coupling to the JFETS. Of course, there is a significant time lag in this coupling, but it could cause some problems for bias balance.
The center of the board could be de-cluttered by moving the cascode circuit to the empty areas away from the center, allowing the JFETs to move to near the power connector.
Another possibility is to move the feedback
Your layouts keep getting better. Good work.
My only concern now is the proximity of the JFETs to the output signal and to the feedback resistors R7-R10. My concern feedback resistors is that their temperature changes dramatically with the output level, and there is likely to be significant thermal coupling to the JFETS. Of course, there is a significant time lag in this coupling, but it could cause some problems for bias balance.
The center of the board could be de-cluttered by moving the cascode circuit to the empty areas away from the center, allowing the JFETs to move to near the power connector.
Another possibility is to move the feedback
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