Hi galeb,
First of all you need an ultra-low jitter clock, and source jitter must be fully blocked. This basically means clocking the TDA1541A directly from the master clock, and either synchronize the source, or synchronize the master clock (VCXO).
I used the following master clock distribution scheme for the latest D1 and D1M DACs:
Master clock > 2 x 47 Ohm in series > 4 x UHS buffer (Fairchild)
UHS buffer # 1 output > 2K2 > SPDIF receiver (receiver in slave clock mode).
UHS buffer # 2 output > TDA1541A / TDA1543 clock input
UHS buffer # 3 output > 3K3 > WS / differential DEM clock divider circuit.
UHS buffer # 4 output > 2K7 > Micro controller clock input (tracker)
I used highest possible damping resistor values for all loads except for the DAC clock in order to minimize the effect of loads polluting the master clock through the clock buffers (parasitic capacitance between both clock buffer input and output).
WS and DATA input signals were attenuated, each input, 3K3 to +5V, 1K to GND, and 3K3 from input to WS / DATA output. This significantly reduces HF interference being dumped on the DAC chip substrate.
DEM clock is driven by an external 352.8 KHz signal. I used both a non-inverted and an inverted 352.8 KHz square wave (derived from a 74HC4040 divider connected to the master clock, and an inverter). Each output connects to 1K2, the other sides of the 1K2 resistors are connected to a 330 Ohm. The attenuated voltage across the 330 Ohm resistor is fed to TDA1541A pins 16 & 17, using two 1nF ceramic NPO capacitors. This ensures a low-jitter DEM clock that runs in sync with the master clock. Using the data sheet DEM clock circuit introduces a second jittery free-running clock of approx. 150 ... 250 KHz that will inter-modulate with the master clock.
The 14 active divider decoupling caps need to attenuate the ripple voltage that is created by passive current divider output mismatch that is part of the active divider. I currently use 1uF for MSB (pin 13 & pin 18), and 100nF for the other MSBs. Some MSBs only have half the ripple current frequency due to active divider construction, this would require 2 different decoupling cap values that average around 100nF, so both 68 and 120nF could be used.
pin 18, 20, 22, and pin 9, 11, and 13 have half the ripple voltage frequency compared to the remaining decoupling pins, so the higher decoupling cap value (120nF from the example) should be used here.
The active divider decoupling caps are just used for that, decoupling, there is no audio frequency running through these caps, just a HF ripple current. The effect on sound quality is caused by how effective the ripple voltage is suppressed. Because of the high frequencies involved, small caps with lowest possible inductance should be used. On the other hand, these caps require very low leakage current in order to prevent bit errors. I use small BC-components 470-series film capacitors, placed very close to the chip. Also consider that any interference current running through decoupling cap GND routes will add to the output signal, so PCB routing is extremely critical.
The I/V converter / amplifier / buffer stage must be tailor-made for the TDA1541A internal circuit. I no longer use OP-amp for this, but prefer discrete circuits without global feedback. I would suggest using simplest possible discrete design with fewest possible components. The key issue is that the DAC outputs a large bandwidth signal, and the following (analogue) stages must remain stable over this entire bandwidth.
The TDA1541A output sinks a constant current. There are 16 static constant current outputs, compare it with 16 separate cascoded constant current sources that simultaneously produce static binary weighted output currents (2mA, 1mA, 0.5mA, 0.25mA, 0.125mA and so on). Diode-transistor bit switches connect each of these current outputs either to the DAC output, or to +5V.
The current outputs will only function correctly when both DC and AC output voltage at the TDA1541A remain close to zero volts. The current can best be converted into a voltage using passive I/V conversion, using an ultra-low noise resistor, and meeting DAC +/-25mV output compliance. The voltage across the I/V resistor must be buffered.
Avoid amplifying the signal across the I/V resistor, as noise will be amplified too.
Finally the power supplies need to be as clean as possible. Try to maximize series impedance to the polluted DC voltage, and minimize shunt impedance across the load. HF-decoupled Cascoded-cascode current sources feeding a shunt regulator with very low impedance is a good start. You could add the charge-transfer power supply to reduce power supply pollution prior to feeding these shunt regulators.
First of all you need an ultra-low jitter clock, and source jitter must be fully blocked. This basically means clocking the TDA1541A directly from the master clock, and either synchronize the source, or synchronize the master clock (VCXO).
I used the following master clock distribution scheme for the latest D1 and D1M DACs:
Master clock > 2 x 47 Ohm in series > 4 x UHS buffer (Fairchild)
UHS buffer # 1 output > 2K2 > SPDIF receiver (receiver in slave clock mode).
UHS buffer # 2 output > TDA1541A / TDA1543 clock input
UHS buffer # 3 output > 3K3 > WS / differential DEM clock divider circuit.
UHS buffer # 4 output > 2K7 > Micro controller clock input (tracker)
I used highest possible damping resistor values for all loads except for the DAC clock in order to minimize the effect of loads polluting the master clock through the clock buffers (parasitic capacitance between both clock buffer input and output).
WS and DATA input signals were attenuated, each input, 3K3 to +5V, 1K to GND, and 3K3 from input to WS / DATA output. This significantly reduces HF interference being dumped on the DAC chip substrate.
DEM clock is driven by an external 352.8 KHz signal. I used both a non-inverted and an inverted 352.8 KHz square wave (derived from a 74HC4040 divider connected to the master clock, and an inverter). Each output connects to 1K2, the other sides of the 1K2 resistors are connected to a 330 Ohm. The attenuated voltage across the 330 Ohm resistor is fed to TDA1541A pins 16 & 17, using two 1nF ceramic NPO capacitors. This ensures a low-jitter DEM clock that runs in sync with the master clock. Using the data sheet DEM clock circuit introduces a second jittery free-running clock of approx. 150 ... 250 KHz that will inter-modulate with the master clock.
The 14 active divider decoupling caps need to attenuate the ripple voltage that is created by passive current divider output mismatch that is part of the active divider. I currently use 1uF for MSB (pin 13 & pin 18), and 100nF for the other MSBs. Some MSBs only have half the ripple current frequency due to active divider construction, this would require 2 different decoupling cap values that average around 100nF, so both 68 and 120nF could be used.
pin 18, 20, 22, and pin 9, 11, and 13 have half the ripple voltage frequency compared to the remaining decoupling pins, so the higher decoupling cap value (120nF from the example) should be used here.
The active divider decoupling caps are just used for that, decoupling, there is no audio frequency running through these caps, just a HF ripple current. The effect on sound quality is caused by how effective the ripple voltage is suppressed. Because of the high frequencies involved, small caps with lowest possible inductance should be used. On the other hand, these caps require very low leakage current in order to prevent bit errors. I use small BC-components 470-series film capacitors, placed very close to the chip. Also consider that any interference current running through decoupling cap GND routes will add to the output signal, so PCB routing is extremely critical.
The I/V converter / amplifier / buffer stage must be tailor-made for the TDA1541A internal circuit. I no longer use OP-amp for this, but prefer discrete circuits without global feedback. I would suggest using simplest possible discrete design with fewest possible components. The key issue is that the DAC outputs a large bandwidth signal, and the following (analogue) stages must remain stable over this entire bandwidth.
The TDA1541A output sinks a constant current. There are 16 static constant current outputs, compare it with 16 separate cascoded constant current sources that simultaneously produce static binary weighted output currents (2mA, 1mA, 0.5mA, 0.25mA, 0.125mA and so on). Diode-transistor bit switches connect each of these current outputs either to the DAC output, or to +5V.
The current outputs will only function correctly when both DC and AC output voltage at the TDA1541A remain close to zero volts. The current can best be converted into a voltage using passive I/V conversion, using an ultra-low noise resistor, and meeting DAC +/-25mV output compliance. The voltage across the I/V resistor must be buffered.
Avoid amplifying the signal across the I/V resistor, as noise will be amplified too.
Finally the power supplies need to be as clean as possible. Try to maximize series impedance to the polluted DC voltage, and minimize shunt impedance across the load. HF-decoupled Cascoded-cascode current sources feeding a shunt regulator with very low impedance is a good start. You could add the charge-transfer power supply to reduce power supply pollution prior to feeding these shunt regulators.
Hi Rick Miller,
I don't, because I generate 2V rms across the I/V resistor. There is no reason to connect the I/V resistor directly to the DAC output, so both, meeting output compliance and generating 2V rms across the I/V resistor is still possible. This approach requires no active amplification, only buffering.
I don't, because I generate 2V rms across the I/V resistor. There is no reason to connect the I/V resistor directly to the DAC output, so both, meeting output compliance and generating 2V rms across the I/V resistor is still possible. This approach requires no active amplification, only buffering.
Hi Rick Miller,
You just need a circuit that presents a low impedance to the DAC output and passes the current to the I/V resistor that's connected to a positive voltage (both TDA1541A and TDA1543 have current sink outputs). This way it's theoretically possible to generate very high output voltages directly across the I/V resistor, while meeting DAC output compliance. The ac voltage across the I/V resistor is basically limited by the low-impedance circuit specs, and could theoretically be well over 100 Vpp using a single DAC chip.
Example:
TDA1543 with 10K I/V resistor would produce 23Vpp
TDA1541A with 10K I/V resistor would produce 40Vpp
TDA1543 with 27K I/V resistor would produce 62.1Vpp
TDA1541A with 27K I/V resistor would produce 108Vpp
Yesterday, during experimenting, I achieved approx. 23 Vpp from a single TDA1543, using a 30V power supply (TDA1543 power supply was set to 5V).
Then I used a simple MOSFET power unity-gain buffer to drive the speaker with up to 23Vpp, the I/V resistor was made variable (10K potentiometer) in order to vary the volume. This configuration produced up to 8.26W rms, the sound was incredibly clean and detailed, regardless of volume setting.
Only problem is that some safety (muting) circuits are required to prevent loud pops / clicks that could occur during power-up or down, or when disconnecting / reconnecting the interlink between both DAC and buffer during operation.
You just need a circuit that presents a low impedance to the DAC output and passes the current to the I/V resistor that's connected to a positive voltage (both TDA1541A and TDA1543 have current sink outputs). This way it's theoretically possible to generate very high output voltages directly across the I/V resistor, while meeting DAC output compliance. The ac voltage across the I/V resistor is basically limited by the low-impedance circuit specs, and could theoretically be well over 100 Vpp using a single DAC chip.
Example:
TDA1543 with 10K I/V resistor would produce 23Vpp
TDA1541A with 10K I/V resistor would produce 40Vpp
TDA1543 with 27K I/V resistor would produce 62.1Vpp
TDA1541A with 27K I/V resistor would produce 108Vpp
Yesterday, during experimenting, I achieved approx. 23 Vpp from a single TDA1543, using a 30V power supply (TDA1543 power supply was set to 5V).
Then I used a simple MOSFET power unity-gain buffer to drive the speaker with up to 23Vpp, the I/V resistor was made variable (10K potentiometer) in order to vary the volume. This configuration produced up to 8.26W rms, the sound was incredibly clean and detailed, regardless of volume setting.
Only problem is that some safety (muting) circuits are required to prevent loud pops / clicks that could occur during power-up or down, or when disconnecting / reconnecting the interlink between both DAC and buffer during operation.
I am using TDA 1541 with 16 bit 8 times oversampling using CS8412, SAA 7220 and 74HCXXXX.
The output stage is 4 x NE 5534 and after which the DC block by 2 x 10uF Solen Fast Cap.
Can I know how to convert to NOS or to the better sampling with DEM? Also what is your comment on the design ?
The output stage is 4 x NE 5534 and after which the DC block by 2 x 10uF Solen Fast Cap.
Can I know how to convert to NOS or to the better sampling with DEM? Also what is your comment on the design ?
Hi ccschua,
Convert the circuit to NOS:
- remove SAA7220.
- U6 pin2 (BCK) to U6 pin 16.
- U6 pin3 (DATA) to U6 pin 15.
- U6 pin1 (WS) to U6 pin 18.
Convert to differential DEM clock:
- Use U1 pin 3 for 352.8 KHz DEM clock
- Remove C19 (470pF).
- Read post #2441 for DEM clock circuit details.
I personally wouldn't use OP-amps. Solen fast caps aren't the best performers, check humble home-made hifi capacitor test:
http://www.humblehomemadehifi.com/Cap.html
There is still room for improvement. You could add I2S attenuators on DATA / WS. The power supply (decoupling) could be improved, 10uF decoupling caps will hardly have any effect, you might increase them to 220 ... 1000uF.
The master clock isn't synchronized with the source clock, either synchronize the source (slave clock operation), or synchronize the master clock (requires VCXO).
I would also increase MSB active divider decoupling capacitor value (U5 pin 13 and pin 18) to 1uF. The OP-amp circuit could be replaced by the circuit published by Rudolf Broertjes.
Convert the circuit to NOS:
- remove SAA7220.
- U6 pin2 (BCK) to U6 pin 16.
- U6 pin3 (DATA) to U6 pin 15.
- U6 pin1 (WS) to U6 pin 18.
Convert to differential DEM clock:
- Use U1 pin 3 for 352.8 KHz DEM clock
- Remove C19 (470pF).
- Read post #2441 for DEM clock circuit details.
I personally wouldn't use OP-amps. Solen fast caps aren't the best performers, check humble home-made hifi capacitor test:
http://www.humblehomemadehifi.com/Cap.html
There is still room for improvement. You could add I2S attenuators on DATA / WS. The power supply (decoupling) could be improved, 10uF decoupling caps will hardly have any effect, you might increase them to 220 ... 1000uF.
The master clock isn't synchronized with the source clock, either synchronize the source (slave clock operation), or synchronize the master clock (requires VCXO).
I would also increase MSB active divider decoupling capacitor value (U5 pin 13 and pin 18) to 1uF. The OP-amp circuit could be replaced by the circuit published by Rudolf Broertjes.
Tks bro, will do the NOS first.
I found this http://diyparadise.com/ssiv.html guess it is the SS IV.
Will do the MSB 1uF mod as well. will change it to polypropelene.
Also I will parallel the 10uF with 100uF Elna Silmic II
I found this http://diyparadise.com/ssiv.html guess it is the SS IV.
Will do the MSB 1uF mod as well. will change it to polypropelene.
Also I will parallel the 10uF with 100uF Elna Silmic II
Just corrected something. The pin 20 of CS8412 was using 10nF and 1k Dale resistor. Now I put in 40nF with 1k resistor. Also I increase the the output cap (parallel the Solen 10uF ) with 100uF ELNA silmic 2.
Now when I listen to music, I was like wow. The sound has leapfrog 1 step higher and most noticeably the bass response becomes more punchy and acoustics last longer with more weight.
tks to ECDesign
Now when I listen to music, I was like wow. The sound has leapfrog 1 step higher and most noticeably the bass response becomes more punchy and acoustics last longer with more weight.
tks to ECDesign
ccschua said:
This I/V was apparently intended for the TDA1543 or 1545: http://www.diyaudio.com/forums/showthread.php?postid=323018#post323018
John
Hi galeb,
The I/V resistor should not be connected directly to the DAC output as this will violate DAC chip ac output compliance.
TDA1541A requires (almost) zero volts ac and dc on the output in order to function correctly.
TDA1543 has a different output circuit and can tolerate higher ac voltages on the output, but for highest performance it's best to keep the dc voltage on the outputs around 2.1V, and meet +/-25mV ac output compliance.
Studying Jocko's I/V converter schematic will provide some tips of how to accomplish this:
> Digital > Easy-to-build I/V stage.
Q1 is configured as a diode that almost matches Q2 be characteristics. The voltage across Q1 will settle around 0.7 volts and should act as a constant voltage source. Q2 is driven into saturation by the DAC bias output current (2mA).
Vbe of Q2 will be (almost) equal to the voltage drop across Q1, so the emitter of Q2 sits around 0V. The saturated Q2 will present a low impedance to the DAC while passing the DAC current through the collector.
Q2 collector ac voltage may vary up to the max. Vce of Q2 (120V), while the DAC output remains at almost zero ac / dc.
When using the TDA1543, the 0.7V reference voltage for Q2 needs to be increased to approx. Vbias + Vbe = 2.1 + 0.7 = 2.8V. Using a LM336-2.5 set at highest voltage (voltage control pin connected to output gives around 2.7V) will do fine, it replaces Q1 in Jocko's schematic.
The I/V resistor should not be connected directly to the DAC output as this will violate DAC chip ac output compliance.
TDA1541A requires (almost) zero volts ac and dc on the output in order to function correctly.
TDA1543 has a different output circuit and can tolerate higher ac voltages on the output, but for highest performance it's best to keep the dc voltage on the outputs around 2.1V, and meet +/-25mV ac output compliance.
Studying Jocko's I/V converter schematic will provide some tips of how to accomplish this:
> Digital > Easy-to-build I/V stage.
Q1 is configured as a diode that almost matches Q2 be characteristics. The voltage across Q1 will settle around 0.7 volts and should act as a constant voltage source. Q2 is driven into saturation by the DAC bias output current (2mA).
Vbe of Q2 will be (almost) equal to the voltage drop across Q1, so the emitter of Q2 sits around 0V. The saturated Q2 will present a low impedance to the DAC while passing the DAC current through the collector.
Q2 collector ac voltage may vary up to the max. Vce of Q2 (120V), while the DAC output remains at almost zero ac / dc.
When using the TDA1543, the 0.7V reference voltage for Q2 needs to be increased to approx. Vbias + Vbe = 2.1 + 0.7 = 2.8V. Using a LM336-2.5 set at highest voltage (voltage control pin connected to output gives around 2.7V) will do fine, it replaces Q1 in Jocko's schematic.
Hi ccschua,
My mistake, I was referring to the 10uF power supply decoupling caps C11, C50, C58, C60, and C64.
But if bypassing the output coupling caps improve perceived sound quality, that's fine too.
LM3x7 series are rather noisy (check datasheet).
The key issue in digital playback systems is inter-modulation between noise / interference and the audio signal.
The very large bandwidth interference from the digital circuits is the major course for this. This interference will always inter-modulate with the audio signal.
The perceived sound quality is greatly influenced by the interference harmonics spectrum that can affect the entire audio range from lowest bass to highest trebles.
My main objective now is isolating the audio signal from all the noise / interference, thus reducing inter-modulation. This has to be done systematically, step by step while closely monitoring the effect of each modification.
My mistake, I was referring to the 10uF power supply decoupling caps C11, C50, C58, C60, and C64.
But if bypassing the output coupling caps improve perceived sound quality, that's fine too.
LM3x7 series are rather noisy (check datasheet).
The key issue in digital playback systems is inter-modulation between noise / interference and the audio signal.
The very large bandwidth interference from the digital circuits is the major course for this. This interference will always inter-modulate with the audio signal.
The perceived sound quality is greatly influenced by the interference harmonics spectrum that can affect the entire audio range from lowest bass to highest trebles.
My main objective now is isolating the audio signal from all the noise / interference, thus reducing inter-modulation. This has to be done systematically, step by step while closely monitoring the effect of each modification.
I/V resistor
Hi ECdesigns,
I've mistaked my reply because I've readed too fast your answer and didn't saw that before the resistor there has to be placed a I/V converter. I've been searching for a discrete one. I think CDA288 from Copland, wich uses 4 PCM63 maybe could be good to start with. I have it's schematics. What do you think?
Regards
PD: for the ps I'm actually using triple regulation and current sources and decoupling chokes from murata, like you did.
Hi ECdesigns,
I've mistaked my reply because I've readed too fast your answer and didn't saw that before the resistor there has to be placed a I/V converter. I've been searching for a discrete one. I think CDA288 from Copland, wich uses 4 PCM63 maybe could be good to start with. I have it's schematics. What do you think?
Regards
PD: for the ps I'm actually using triple regulation and current sources and decoupling chokes from murata, like you did.
I switch as u say
remove SAA7220.
- U6 pin2 (BCK) to U6 pin 16.
- U6 pin3 (DATA) to U6 pin 15.
- U6 pin1 (WS) to U6 pin 18.
Now I am in the NOS mood. (mode ?) The details is super and more body. very surprise at the details, but the poor record cd sound harsh.
Oh ECDesign, u are the god here. I trust your works.
remove SAA7220.
- U6 pin2 (BCK) to U6 pin 16.
- U6 pin3 (DATA) to U6 pin 15.
- U6 pin1 (WS) to U6 pin 18.
Now I am in the NOS mood. (mode ?) The details is super and more body. very surprise at the details, but the poor record cd sound harsh.
Oh ECDesign, u are the god here. I trust your works.
charge transfer power and SPDIF
Hi John (ECdesigns)
Charge Tranfer Power question.
----------------------------------------
the 11DQ10 has a junction capacitance of 35 Pf
The 2SK 2391 180 pf (drain source)
The 2SJ380 200 pf
In serie this is about 10 pf and that capacitance is always there.
70 pf (D1+D2) - 35 pf (D3) - 200 pf (T1) - 180 pf (T2)
A capacitance big enough to let pass all the HF **** from the AC powerline.
There are rectifiers with a junction capacitance < 1 pf.
Do I see that OK or are you measuring an other capacitance between te transformer coil and point + ?
Bit perfect SPDIF Question
---------------------------------
How are you measuring (comparing) bit perfect pass trough spdif.
(I know the DTS trick)
And for you and all of you (a bit late but not to late) a prosperous 2009.
Onno
Hi John (ECdesigns)
Charge Tranfer Power question.
----------------------------------------
the 11DQ10 has a junction capacitance of 35 Pf
The 2SK 2391 180 pf (drain source)
The 2SJ380 200 pf
In serie this is about 10 pf and that capacitance is always there.
70 pf (D1+D2) - 35 pf (D3) - 200 pf (T1) - 180 pf (T2)
A capacitance big enough to let pass all the HF **** from the AC powerline.
There are rectifiers with a junction capacitance < 1 pf.
Do I see that OK or are you measuring an other capacitance between te transformer coil and point + ?
Bit perfect SPDIF Question
---------------------------------
How are you measuring (comparing) bit perfect pass trough spdif.
(I know the DTS trick)
And for you and all of you (a bit late but not to late) a prosperous 2009.
Onno