Hi luxury54,
16.9344 MHz equals 384 * fs, 384 * 44,100 = 16.9344 MHz.
11.2896 MHz equals 256 * fs, 256 * 44,100 = 11.2896 MHz
The difference between both frequencies equals 384 / 256 = 1.5.
One possible solution, first divide 11.2896 MHz by 2, then feed it to a multiplier (PLL) that multiplies this frequency with 3.
11,289,600 / 2 = 5,644,800
5,644,800 * 3 = 16,934,400
The 16,934,400 MHz signal that's derived from the 11,289,600 MHz masterclock (and runs in sync with the masterclock) can now be used to slave the transport.
16.9344 MHz equals 384 * fs, 384 * 44,100 = 16.9344 MHz.
11.2896 MHz equals 256 * fs, 256 * 44,100 = 11.2896 MHz
The difference between both frequencies equals 384 / 256 = 1.5.
One possible solution, first divide 11.2896 MHz by 2, then feed it to a multiplier (PLL) that multiplies this frequency with 3.
11,289,600 / 2 = 5,644,800
5,644,800 * 3 = 16,934,400
The 16,934,400 MHz signal that's derived from the 11,289,600 MHz masterclock (and runs in sync with the masterclock) can now be used to slave the transport.
Hi gaetan888,
When running a CS8412/14/16 in slave clock mode without further synchronization, perceived sound quality is very good. But when playing back sine wave test signals, periodic clicks are audible. When listening to music, these clicks are almost inaudible as they are masked by the music content, but with specific tones (pure sine wave tones) from either voices or instruments, the clicks become audible.
Slaving a transport is rather difficult, first it's best to avoid any galvanic or capacitive coupling between both source and DAC. Second, loads connected to a (buffered) master clock output can affect master clock jitter performance. So you could have a pretty good master clock with say 10ps rms jitter in the audio range, but when you connect required loads, you could end up with 100ps rms. So simply buffering the master clock, and feeding it back to the source using a coax interlink, could result in significant increase of master clock jitter. So the DAC connected to the master clock still receives a jittery timing signal despite being located close to the master clock.
If I had to slave a transport, I would divide the low jitter master clock to a frequency that's well within Toslink bandwidth (approx. 10 MHz). Next I would send it to the transport using Toslink interlink. In the transport I would multiply the clock using a PLL. The derived clock would run in sync with the master clock, and has higher jitter, but since it's only used to drive the transport electronics -not the DAC chip- this should be acceptable.
Using the example in post #2482, the 11.2896 MHz master clock in the DAC is divided by 2 (5.6448 MHz), sent over the Toslink to the transport. In the transport, the received clock signal is multiplied by 3, deriving the required 16.9344 MHz master clock.
Second Toslink interconnect is used for sending the SPDIF signal from the transport to the DAC, so two Toslink interlinks are required. This provides required zero coupling capacitance and 100% galvanic insulation between both transport and DAC.
When running a CS8412/14/16 in slave clock mode without further synchronization, perceived sound quality is very good. But when playing back sine wave test signals, periodic clicks are audible. When listening to music, these clicks are almost inaudible as they are masked by the music content, but with specific tones (pure sine wave tones) from either voices or instruments, the clicks become audible.
Slaving a transport is rather difficult, first it's best to avoid any galvanic or capacitive coupling between both source and DAC. Second, loads connected to a (buffered) master clock output can affect master clock jitter performance. So you could have a pretty good master clock with say 10ps rms jitter in the audio range, but when you connect required loads, you could end up with 100ps rms. So simply buffering the master clock, and feeding it back to the source using a coax interlink, could result in significant increase of master clock jitter. So the DAC connected to the master clock still receives a jittery timing signal despite being located close to the master clock.
If I had to slave a transport, I would divide the low jitter master clock to a frequency that's well within Toslink bandwidth (approx. 10 MHz). Next I would send it to the transport using Toslink interlink. In the transport I would multiply the clock using a PLL. The derived clock would run in sync with the master clock, and has higher jitter, but since it's only used to drive the transport electronics -not the DAC chip- this should be acceptable.
Using the example in post #2482, the 11.2896 MHz master clock in the DAC is divided by 2 (5.6448 MHz), sent over the Toslink to the transport. In the transport, the received clock signal is multiplied by 3, deriving the required 16.9344 MHz master clock.
Second Toslink interconnect is used for sending the SPDIF signal from the transport to the DAC, so two Toslink interlinks are required. This provides required zero coupling capacitance and 100% galvanic insulation between both transport and DAC.
-ecdesigns- said:
Dear John,
Thank you for your kindly response.
I wanted to ask you if you know such a 3X clock frequency multiplier (electronic part) that goes up to 17 mhz and i can use here, and maybe you had some experience how to set it's PLL and surrounding circuit to work for this kind of needs
p.s.
I was google-ing for this frequency multiplier and someone with the same problem like mine, came up and put up a question what does he need to solve this multiplication...then the answer came:
"even if you make such a circuit the jitter on the output will be higher than the original clock,because they reconstruct (a bit like the CS8412 does) the higher frequency clock multiple using a PLL."
so I'm wondering if it's worth it,and if i will have any benefit on this,or maybe i should throw away that 16.934 mhz transport and get myself one with 11.2896 ?
@luxury54
http://www.onsemi.com/PowerSolutions/product.do?id=NB3N502
simple pll 3x (also 2, 4, 5, 2.5, 3.33 - hw selectable) clock multiplier
ciao
andrea
http://www.onsemi.com/PowerSolutions/product.do?id=NB3N502
simple pll 3x (also 2, 4, 5, 2.5, 3.33 - hw selectable) clock multiplier
ciao
andrea
Hi luxury54
The derived 16.9344 clock with higher jitter is only used to clock the CD player, NOT the DAC chip. The DAC chip receives a (ultra) low jitter clock, derived from the 11.2896 MHz master clock.
ICS502 (Microclock / TI / IDT / ICS), x2, x5, x3, x3.3, x4, x2.5 (input clock frequency 5 ... 50 Mc / output up to 190 MHz).
The derived 16.9344 clock with higher jitter is only used to clock the CD player, NOT the DAC chip. The DAC chip receives a (ultra) low jitter clock, derived from the 11.2896 MHz master clock.
ICS502 (Microclock / TI / IDT / ICS), x2, x5, x3, x3.3, x4, x2.5 (input clock frequency 5 ... 50 Mc / output up to 190 MHz).
cheers John,
I am starting to collect the parts needed for the DEM reclock - I already have the parts to upgrade to the Charge Transfer PS, so I have plenty to keep me busy for now.
I have a couple of 74HC4040 ICs - are these suitable for use in the DEM reclock? Or do i really need to get the HCT version?
Brad
I am starting to collect the parts needed for the DEM reclock - I already have the parts to upgrade to the Charge Transfer PS, so I have plenty to keep me busy for now.
I have a couple of 74HC4040 ICs - are these suitable for use in the DEM reclock? Or do i really need to get the HCT version?
Brad
Hi John,
I have just updated the charge transfer schematic to show the connections for transformers without the centre tap - is this the correct way to connect these?
I have also just added the sugested attenuation on the WS and data signals and have now got a problem with the output on the right channel - after about 5 minutes of playback the right channel starts to distort. I may have altered something else, but I think it may be caused by the attenuation scheme.
Brad
I have just updated the charge transfer schematic to show the connections for transformers without the centre tap - is this the correct way to connect these?
I have also just added the sugested attenuation on the WS and data signals and have now got a problem with the output on the right channel - after about 5 minutes of playback the right channel starts to distort. I may have altered something else, but I think it may be caused by the attenuation scheme.
Brad
Attachments
Hi Builder Brad,
You need to use a rectifier bridge (requires 4 rectifier diodes).
This is probably caused by tolerances, as the DAC chip heats-up, the voltage across the internal diodes (digital input circuit) drops. This can be solved by lowering the series resistor value, you could try 2K2 or lower.
You need to use a rectifier bridge (requires 4 rectifier diodes).
This is probably caused by tolerances, as the DAC chip heats-up, the voltage across the internal diodes (digital input circuit) drops. This can be solved by lowering the series resistor value, you could try 2K2 or lower.
Hi Telstar,
I planned to support 44.1 KHz sample rate only, I used 11.2896 MHz because of availability of required crystal.
Then I ran into troubles with my satellite receiver that outputs 48 KHz sample rate.
Today this problem was fixed.
My brother successfully completed the firmware for the new multi-rate master clock / tracker module.
This micro controller-based multi-rate tracker / master clock module automatically detects and tracks 44.1 KHz, 48 KHz, 88.2 KHz, and 96 KHz sample rates. It uses 2 crystals (11.2896 and 12.288 MHz), and a programmable clock divider to support these sample rates.
So I now have a highly effective source jitter blocker that accepts 44.1, 48, 88.2, and 96 KHz sample rates. These sample rates are supported by Toslink, and are within TDA1541A / TDA1543 bit clock specs.
I planned to support 44.1 KHz sample rate only, I used 11.2896 MHz because of availability of required crystal.
Then I ran into troubles with my satellite receiver that outputs 48 KHz sample rate.
Today this problem was fixed.
My brother successfully completed the firmware for the new multi-rate master clock / tracker module.
This micro controller-based multi-rate tracker / master clock module automatically detects and tracks 44.1 KHz, 48 KHz, 88.2 KHz, and 96 KHz sample rates. It uses 2 crystals (11.2896 and 12.288 MHz), and a programmable clock divider to support these sample rates.
So I now have a highly effective source jitter blocker that accepts 44.1, 48, 88.2, and 96 KHz sample rates. These sample rates are supported by Toslink, and are within TDA1541A / TDA1543 bit clock specs.
THANK-YOU JOHN,
"You need to use a rectifier bridge (requires 4 rectifier diodes)"
I thought that your schematic was giving half wave rectification - providing plenty of time for the mosfets to switch and transfer the charge - looking at the details again I can see that the centre tapped transformer is also connected up for full wave rectification.
congratulations on you solution, regards the sample rate input firmware.
"You need to use a rectifier bridge (requires 4 rectifier diodes)"
I thought that your schematic was giving half wave rectification - providing plenty of time for the mosfets to switch and transfer the charge - looking at the details again I can see that the centre tapped transformer is also connected up for full wave rectification.
congratulations on you solution, regards the sample rate input firmware.
-ecdesigns- said:
Hello John
I can not have the CS8412 or CS8414 here arround and buying them from out of Canada would cost way too much with the shipping.
But I can have the AK4114, AK4116, AK4117, WM8804 (very low jitter), DIR9001 (very low jitter), or maby the CS8416.
Do I really need to use the receiver master with a clock/tracker module and in slave mode ?
Maby I could do could do a simplier version of the DI4 with one of the receiver that I can have ?
Thank
Bye
Gaetan
Hi John,
You need to use a rectifier bridge (requires 4 rectifier diodes).
I had prepared such a circuit with a full bridge rectifier that I intended to use.
To return to your original circuit we only need to remove D3, D4 and add the jumper.
This way we can use a transformer with center tap or a single winding.
I also worked on a pcb for this circuit. I still need to ajust the footprints for various capacitors to use.
I would appreciate you check it out, if it would be usefull to others on this thread.
You need to use a rectifier bridge (requires 4 rectifier diodes).
I had prepared such a circuit with a full bridge rectifier that I intended to use.
To return to your original circuit we only need to remove D3, D4 and add the jumper.
This way we can use a transformer with center tap or a single winding.
I also worked on a pcb for this circuit. I still need to ajust the footprints for various capacitors to use.
I would appreciate you check it out, if it would be usefull to others on this thread.
Hi gaetan8888,
Both AK4114, and WM8804 support slave-clock mode and seem to be suitable. I use the CS8416, it's placed on a module, so I could easily swap between various SPDIF receiver chips.
Depends on the sound quality you want to achieve, I tried many different solutions. I started with a CS8412 in master mode (coax and RS422 twisted pair), and experimented with direct I2S (DATA, CLOCK and WS signals transmitted using 3 x RS422 twisted-pair).
Next I tried USB / direct I2S, using an asynchronous reclocker (USBDI2S module), later an USB / Toslink combination module was designed (UTOS1 & 2), I2S signals from USB were routed through high-speed opto-couplers, and SPDIF was routed through Toslink. Asynchronous reclockers were used to attenuate source jitter. During these experiments, the advantages of full galvanic insulation became clear.
Then I experimented with running a SPDIF receiver in slave-clock mode, directly feeding the crystal oscillator signal to the DAC chips. This was a big improvement, but the lack of synchronization between both source and master clock produced audible cliks, best audible when playing-back sine waves.
In order to solve the synchronization issue, I then experimented with a VCXO / PLL circuit, this circuit was first used in both DI4T and DI4MJ, and it was integrated on the mainboard. The clicks were gone, but still sound quality wasn't optimal.
So I decided to replace the analogue PLL with a micro controller-based frequency tracker that only performs corrections with 2 second intervals. This solution works fine, and I designed a PCB that holds master clock, tracker and clock buffers.
In order to expand the functionality of this tracker circuit, a multi-sample rate support was added, so the tracker could be used with popular sample rates. It would also be possible to support 176.4 and 192 KHz, using the same 2 crystals. This possible option will be included in the new design. In that case the tracker could automatically detect and track 44.1, 48, 88.2, 96, 176.4, and 192 KHz.
Both AK4114, and WM8804 support slave-clock mode and seem to be suitable. I use the CS8416, it's placed on a module, so I could easily swap between various SPDIF receiver chips.
Depends on the sound quality you want to achieve, I tried many different solutions. I started with a CS8412 in master mode (coax and RS422 twisted pair), and experimented with direct I2S (DATA, CLOCK and WS signals transmitted using 3 x RS422 twisted-pair).
Next I tried USB / direct I2S, using an asynchronous reclocker (USBDI2S module), later an USB / Toslink combination module was designed (UTOS1 & 2), I2S signals from USB were routed through high-speed opto-couplers, and SPDIF was routed through Toslink. Asynchronous reclockers were used to attenuate source jitter. During these experiments, the advantages of full galvanic insulation became clear.
Then I experimented with running a SPDIF receiver in slave-clock mode, directly feeding the crystal oscillator signal to the DAC chips. This was a big improvement, but the lack of synchronization between both source and master clock produced audible cliks, best audible when playing-back sine waves.
In order to solve the synchronization issue, I then experimented with a VCXO / PLL circuit, this circuit was first used in both DI4T and DI4MJ, and it was integrated on the mainboard. The clicks were gone, but still sound quality wasn't optimal.
So I decided to replace the analogue PLL with a micro controller-based frequency tracker that only performs corrections with 2 second intervals. This solution works fine, and I designed a PCB that holds master clock, tracker and clock buffers.
In order to expand the functionality of this tracker circuit, a multi-sample rate support was added, so the tracker could be used with popular sample rates. It would also be possible to support 176.4 and 192 KHz, using the same 2 crystals. This possible option will be included in the new design. In that case the tracker could automatically detect and track 44.1, 48, 88.2, 96, 176.4, and 192 KHz.
-ecdesigns- said:
Hello John
I would like to keep it as simple as possible and I'm limited in my budget, at least I have the four TDA1541 chip.
I just done a search in the forum and found in your thread a sync reclock post and schematic;
http://www.diyaudio.com/forums/showthread.php?postid=1317660#post1317660
And the schematic link;
http://www.diyaudio.com/forums/attachment.php?s=&postid=1317660&stamp=1191570449
Any littles mod suggestions on this schematic ?
How about using it for the DI4 dac ?
Thank you
Bye
Gaetan