Bob Cordell Interview: Error Correction

[jan.didden]

Andy,

There are some other aspects to this. In Bob's amp, for example, the ec loop encloses only the output devices. The concept however would expect that the correction signal at the ec transistor collector would be transmitted linearly to the gates of the output devices, which is not the case.

This can be improved by picking off the 'signal at the input of the output stage' from the base of the driver or even the predriver rather than the gate of the output mosfet. In that way, the whole output triplet becomes the 'N' stage, and the influence of the load impedance is greatly reduced. Also, the correction in the Rc to compensate for the nonlinearity of the (pre) drivers in the ec forward path is no longer required. EC dynamic range requirements would be reduced.

Jan Didden

 

[Bob Cordell]

Hi Bob,

You can show with a block diagram and calculations that if you put a voltage divider in this path with a "gain" of, say, K1 (where K1 < 1), then the EC diff amp collector resistors must be increased by a factor of 1/K1 to get the optimum error cancellation.

Let's say you have an accurate sim of the output stage, and you measure the large-signal gain of the output stage to be K1. Then if the voltage divider "gain" is also K1, and the EC diff amp gain is set up correctly, you can show that the error signal consists almost entirely of distortion. This is a good thing, as it optimizes the dynamic range of the EC circuitry itself. You've probably observed in sim or on the bench that when the EC dynamic range is exceeded, the distortion becomes quite bad - much worse than if there is no EC. So it's a good idea to optimize the dynamic range of the EC.

But since the output stage gain is dependent on the load, what load impedance should the EC dynamic range be optimized for? I thought about this for a while, and started thinking about the Stereophile amplifier tests. They do power and distortion measurements down to a 2 Ohm load. If you optimize EC dynamic range for a 2 Ohm load, then for higher and lower impedances than 2 Ohms, the error signal amplitude increases due to the gain correction. This can give a surprisingly high error signal with an open circuit load. So I decided to optimize the EC such that with a 2 Ohm load and an open circuit load, the amplitude of the error signals would be equal (but opposite polarity, because in one case the EC is decreasing the gain, and in the other it's increasing it). This is roughly equivalent to optimizing it for a 4 Ohm load, which seems reasonable. Forcing the gain to exactly 1 is nearly the same as optimizing the EC dynamic range for an open circuit load. We can do better.

If one is trying to design an EC amp with output currents approaching what John Curl's JC-1 is capable of, one finds that it's necessary to both increase the DC voltage drop across the EC collector resistors as much as possible, and to do some kind of EC dynamic range optimization as well. Otherwise, with the very low impedances used in output current tests, the EC error signal will become unmanageably large - at least with a MOSFET output stage. The required voltage divider ends up being a very good place to put the distortion nulling pot as well.

Hi Andy,

Welcome back!

These are very good insights and I agree with what you have said, especially about being mindful of EC dynamic range considerations. It is also worth noting that some EC circuits may be better behaved when they run out of EC dynamic range than others.

I also remember that I did extraordinarily brutal 2-cycle sinewave bursts into a 1-ohm load at 20 kHz with my original 50 Watt MOSFET EC amp (which only had a single pair of output MOSFETs). I think it was hitting 22-Amp peaks into the load (scope photos in my paper at www.cordellaudio.com). I don't recall seeing any uglies on the sine burst, but I honestly don't know if the EC was running out of dynamic range in making those high currents.

What I DO remember is that I did the bursts at 20 kHz and everything was fine. Then I foolishly tried to do the stunt for a 2-cycle 20 Hz burst and the thing blew up! It apparently did not have enough SOA to survive the longer cycle time.

I would point out that if one is trying to do a design with extremely high output current capability, one will probably have a good number of output pairs in parallel, with some decent idle bias running through it, so that the gain factor of that output stage will probably be closer to unity even into fairly small loads like 2 ohms.

Cheers,
Bob

 

[andy_c]

This can be improved by picking off the 'signal at the input of the output stage' from the base of the driver or even the predriver rather than the gate of the output mosfet. In that way, the whole output triplet becomes the 'N' stage, and the influence of the load impedance is greatly reduced. Also, the correction in the Rc to compensate for the nonlinearity of the (pre) drivers in the ec forward path is no longer required. EC dynamic range requirements would be reduced.

Hi Jan,

In my present design, I do pick off the input signal of the output stage at the driver input (they are MOSFET drivers). In this way, the EC compensates for the distortion of the drivers as well as the output stage. But without EC, the gain from the driver gates to the output is still very much a function of the load. This is unavoidable.

The way I do this is as follows. Instead of a single resistor between the driver gates (the sources of the predriver JFETs), I put two equal resistors in series. Then, at the junction of these resistors, I put a resistance to ground. This forms a voltage divider network which compensates for the output stage gain being less than 1. Then it's necessary to scale the EC diff amp gain up by the reciprocal of the voltage divider ratio in order to provide the best error cancellation. In other words, optimum EC occurs when the product of the voltage divider ratio and the diff amp gain is 1. If the voltage divider ratio exactly matches the combined driver and output stage gain at some particular load impedance and output signal level, the error signal consists of only distortion, with no fundamental component.

The resistance to ground mentioned above is actually the series combination of a fixed resistor and a pot. The pot is to make up for gain errors in the EC diff amp such that the product of the voltage divider ratio and the diff amp gain is trimmed to be as close to 1 as possible. So it adjusts for the distortion minimum.

 

[traderbam]

Bob wrote:

The error correction view of HEC is like the dual of more conventional feedforward error correction. Indeed, if the measured error of the output stage is fed forward (instead of fed back) and summed with the output, the same distortion reduction and distortion spectrum will result as with HEC if the error measuring bandwidth is the same.

Bob, I thought you meant you had some explanation of your test set-up and measurements in your 1984 AES paper. I didn't find it. I can't comment on whether the observation you mention is significant or pertinent without any detail.

 

[andy_c]

I also remember that I did extraordinarily brutal 2-cycle sinewave bursts into a 1-ohm load at 20 kHz with my original 50 Watt MOSFET EC amp (which only had a single pair of output MOSFETs). I think it was hitting 22-Amp peaks into the load (scope photos in my paper at www.cordellaudio.com). I don't recall seeing any uglies on the sine burst, but I honestly don't know if the EC was running out of dynamic range in making those high currents.

22 A peak with a single pair of output devices is pretty amazing indeed! I should have mentioned that the sims I was doing for the high-current condition were for just the output stage by itself, so there was no global feedback to clean things up.

What I DO remember is that I did the bursts at 20 kHz and everything was fine. Then I foolishly tried to do the stunt for a 2-cycle 20 Hz burst and the thing blew up! It apparently did not have enough SOA to survive the longer cycle time.

I've been working on a protection circuit that uses multipliers and a filter to emulate the thermal transient response of the output devices. The idea is to estimate the instantaneous junction temperature and shut the amp down based on that. Looking at sims of this, it appears that 20 Hz into low impedances is a brutal test of thermal capability. At that low a frequency, the instantaneous junction temperature is essentially following the instantaneous power dissipation. At 20 kHz, there's lots of averaging of the instantaneous power going on, giving much lower peak junction temperatures and much higher current capability without shutdown.

I would point out that if one is trying to do a design with extremely high output current capability, one will probably have a good number of output pairs in parallel, with some decent idle bias running through it, so that the gain factor of that output stage will probably be closer to unity even into fairly small loads like 2 ohms.

Yes, I'm looking at 10+10 output devices (upped from the original estimate of 7+7). Even with this many output devices, it appears the maximum instantaneous junction temperature of the output devices would be exceeded for a full power 20 Hz test into 2 Ohms. I could do a lot better with aluminum oxide insulators, but I'm afraid rework would become a nightmare. Since I'm somewhat of a klutz, I'm sticking with mica and grease .

Even though the gain will be pretty close to unity even for low impedance loads, the error amplitude is roughly proportional to output voltage/current amplitude. So if the amp is putting out, say, 70 Volts peak into 0.68 Ohms, the error can get pretty large - even with lots of output devices.

 

[traderbam]

Bob, while we are on the subject, I just want to make sure I understand you. I infer from your post 2277 (your 3 views) that the error in the output stage can be cancelled out completely in theory using EC, just like it could be in a feedforward system, assuming correct phase an amplitude of the error signal (the dual of feed-forward). And that in both cases this is a cancellation effect as opposed to an "iterative" reduction like in a conventional NFB loop.
Is this your position?
Brian

 

[GK]

If one is trying to design an EC amp with output currents approaching what John Curl's JC-1 is capable of, one finds that it's necessary to both increase the DC voltage drop across the EC collector resistors as much as possible, and to do some kind of EC dynamic range optimization as well. Otherwise, with the very low impedances used in output current tests, the EC error signal will become unmanageably large - at least with a MOSFET output stage. The required voltage divider ends up being a very good place to put the distortion nulling pot as well.

Not so much a problem with BJTs, than with MOSFETs.
With BJT's the required EC dynamic range is essentially just governed by the voltage drop developed across the emitter ballast resistors. Another advantage is that this voltage is much more linearly proportional to the collector / load current, than is the Vgs Vs Id characteristic of a MOSFET.

Cheers,
Glen

 

[andy_c]

Not so much a problem with BJTs, than with MOSFETs.
With BJT's the required EC dynamic range is essentially just governed by the voltage drop developed across the emitter ballast resistors. Another advantage is that this voltage is much more linearly proportional to the collector / load current, than is the Vgs Vs Id characteristic of a MOSFET.

Yes, I agree - which is why I put the MOSFET disclaimer in there . I guess the tradeoff here is that with BJTs it looks like you need supply-referenced EC circuitry like what you have on your pages. Otherwise, it seems you could run into a problem with "Vce crowding" of the EC diff amps.

 

[GK]

Yes, I agree - which is why I put the MOSFET disclaimer in there . I guess the tradeoff here is that with BJTs it looks like you need supply-referenced EC circuitry like what you have on your pages. Otherwise, it seems you could run into a problem with "Vce crowding" of the EC diff amps.

True, but Hawksford’s “figure 5” circuit (from his EC paper) as modified slightly by Bob for his vertical MOSFET output stage can be easily modified to avoid this problem when used with BJT outputs.
The circuit modification I came up with puts an additional pair of resistors in series with the existing pair of collector resistors for the EC circuit, with the EC BJT collectors connected in between. The resistors on the output stage side are each bypassed for HF with capacitor and a constant current is forced through them by returning the base of each EF driver transistor to the opposite supply rail via a constant current source. Now the collectors of each EC transistor idle at +/-5V with respect to the output with no load current.

Cheers,
Glen

 

[andy_c]

True, but Hawksford’s “figure 5” circuit (from his EC paper) as modified slightly by Bob for his vertical MOSFET output stage can be easily modified to avoid this problem when used with BJT outputs.
The circuit modification I came up with puts an additional pair of resistors in series with the existing pair of collector resistors for the EC circuit, with the EC BJT collectors connected in between. The resistors on the output stage side are each bypassed for HF with capacitor and a constant current is forced through them by returning the base of each EF driver transistor to the opposite supply rail via a constant current source. Now the collectors of each EC transistor idle at +/-5V with respect to the output with no load current.

This sounds interesting. I'd like to see the schematic when available, as it seems like you may have changed it since the last time I saw it. I'm currently getting a "not found" error on your web link button.

 

[GK]

This sounds interesting. I'd like to see the schematic when available, as it seems like you may have changed it since the last time I saw it. I'm currently getting a "not found" error on your web link button.

Oh no, I actually went with the supply rail referenced circuit in the end as you recall. This was done out of a preference to keep the temperature compensation circuirty independant of the EC circuitry. The circuit you saw has been changed, but only with respect to the devices used in the output stage and the number of them.
My web site is down ATM, being updated and maybe a change of ISP. It won't be back for a while.

Cheers,
Glen

 

[andy_c]

Oh no, I actually went with the supply rail referenced circuit in the end as you recall. This was done out of a preference to keep the temperature compensation circuirty independant of the EC circuitry.

Ah, I see. I remember looking at your supply-referenced circuit and noticing that it also eliminated another concern I had relative to EC with BJTs - namely keeping the output stage bias current from being affected by possible drifts in the bias currents of the EC transistors. Of course, MOSFETs have this concern also, but somewhat less so due to the smaller gm.

If you can't fix it - feature it! (that is, the low gm of MOSFETs).

 

[GK]

Hey, here is a quick drawing of the mod I described.

Cheers,
Glen

 

[andy_c]

Hey, here is a quick drawing of the mod I described.

Thanks for posting that. Now I see why you went with the supply-referenced EC. Bias current stability of the output stage will be much better with your latest supply-referenced EC.

I ended up going with MOSFETs because I couldn't figure out the output stage bias current stability and Vce crowding problems of the EC, both of which you've solved with your most recent circuits.

 

[GK]

Thanks for posting that. Now I see why you went with the supply-referenced EC. Bias current stability of the output stage will be much better with your latest supply-referenced EC.

I ended up going with MOSFETs because I couldn't figure out the output stage bias current stability and Vce crowding problems of the EC, both of which you've solved with your most recent circuits.

Actually I think that this circuit still would have been OK, since I am applying the EC to a class A output stage, which is inherently much more thermally stable than a class B stage due to the relatively high voltage developed across the emitter ballast resistors, but I still didn’t like it anyway

Cheers,
Glen

 

[jan.didden]

Hi Jan,

In my present design, I do pick off the input signal of the output stage at the driver input (they are MOSFET drivers). In this way, the EC compensates for the distortion of the drivers as well as the output stage. But without EC, the gain from the driver gates to the output is still very much a function of the load. This is unavoidable.
[snip]

Yes indeed, agreed. The 'only' advantage is to include (pre) drivers in the ec loop.

[snip]This forms a voltage divider network which compensates for the output stage gain being less than 1. Then it's necessary to scale the EC diff amp gain up by the reciprocal of the voltage divider ratio in order to provide the best error cancellation. In other words, optimum EC occurs when the product of the voltage divider ratio and the diff amp gain is 1. If the voltage divider ratio exactly matches the combined driver and output stage gain at some particular load impedance and output signal level, the error signal consists of only distortion, with no fundamental component.
[snip]

Andy,

This is something I have also been looking at. While tuning the attenuator and the compensation gain you can indeed get a distortion minimum, this minimum will most probably not be as deep as when you leave out the attenuator and the compensation gain. In theory, you actually lose the distortion null, but in practise the difference may not be that large.

I guess the attached is the concept of what you propose. If you now work out Vout/Vin you get:

Vout/Vin = N/(1-P.Q+N.Q), with N the non-lin gain block you want to compensate, P the attenuator and Q the compensation gain.
It's obvious that N drops out only if Q=1 AND Q.P=1, so both the attenuator and the compensation gain should always be 1 for distortion cancellation.

Jan Didden

 

[GK]

Actually I think that this circuit still would have been OK, since I am applying the EC to a class A output stage, which is inherently much more thermally stable than a class B stage due to the relatively high voltage developed across the emitter ballast resistors, but I still didn’t like it anyway

Cheers,
Glen

Also, so as to not compromise the bias thermal stability in a class B or AB design this circuit modification could be used, but with the two bypassed resistors I added replaced with a pair of voltage reference IC's such as LM336-5 or similar.

Cheers,
Glen

 

[Bob Cordell]

Bob wrote:
Bob, I thought you meant you had some explanation of your test set-up and measurements in your 1984 AES paper. I didn't find it. I can't comment on whether the observation you mention is significant or pertinent without any detail.

Hi Brian,

My statement:

"The error correction view of HEC is like the dual of more conventional feedforward error correction. Indeed, if the measured error of the output stage is fed forward (instead of fed back) and summed with the output, the same distortion reduction and distortion spectrum will result as with HEC if the error measuring bandwidth is the same."

was based on simulations done recently, not on anything I presented in my 1984 AES paper. I apologize for any confusion. Note that feeding the error forward, as in conventional feedforward error correction, is actually quite difficult to do properly in practice, but is easily done in simulation. The point was to show that the overall behavior is the same, whether we are using error feedback (HEC) or error feedforward.

Cheers,
Bob

 

[Bob Cordell]

Bob, while we are on the subject, I just want to make sure I understand you. I infer from your post 2277 (your 3 views) that the error in the output stage can be cancelled out completely in theory using EC, just like it could be in a feedforward system, assuming correct phase an amplitude of the error signal (the dual of feed-forward). And that in both cases this is a cancellation effect as opposed to an "iterative" reduction like in a conventional NFB loop.
Is this your position?
Brian

Yes.

But remember, those are VERY big caveats in practice. Satisfying those caveats is the equivalent of having infinite forward gain and bandwidth in the "feedback" view.

Cheers,
Bob

 

[Bob Cordell]

Not so much a problem with BJTs, than with MOSFETs.
With BJT's the required EC dynamic range is essentially just governed by the voltage drop developed across the emitter ballast resistors. Another advantage is that this voltage is much more linearly proportional to the collector / load current, than is the Vgs Vs Id characteristic of a MOSFET.

Cheers,
Glen

It's not that bad with MOSFETs. If you want to put out 90 Amps with 9 MOSFET output pairs, each with a 0.1 ohm RS, then each MOSFET needs to put out 10A. This typically takes only about 2-3V more than the bias Vgs. Then, 1 V will be dropped on the RS. Bottom line is that you need to have the EC be able to swing 3-4V peak to handle it. Check out the IRFP240 spec sheet.

Cheers,
Bob