Bob Cordell Interview: Error Correction

Bob Cordell said:


.... The point was to show that the overall behavior is the same, whether we are using error feedback (HEC) or error feedforward.

Cheers,
Bob


Bob,

I am afraid the casual reader may be led to the conclusion feddback and feedforward error correction schemes are equivalent as much as results (as per simulation) are similar. Sure this is not what you mean.

Rodolfo

PS. By the way, did you notice this post ?
 
G.Kleinschmidt said:



True, but Hawksford’s “figure 5” circuit (from his EC paper) as modified slightly by Bob for his vertical MOSFET output stage can be easily modified to avoid this problem when used with BJT outputs.
The circuit modification I came up with puts an additional pair of resistors in series with the existing pair of collector resistors for the EC circuit, with the EC BJT collectors connected in between. The resistors on the output stage side are each bypassed for HF with capacitor and a constant current is forced through them by returning the base of each EF driver transistor to the opposite supply rail via a constant current source. Now the collectors of each EC transistor idle at +/-5V with respect to the output with no load current.

Cheers,
Glen


I agree. There are numerous ways to make the EC work with BJTs and give the EC circuit adequate headroom. Most of these ways are no more painful than what must be done when using MOSFETs. Once you bite the bullet and use boosted supplies for the VAS, this is pretty straightforward.

Cheers,
Bob
 
Bob Cordell said:

.... The point was to show that the overall behavior is the same, whether we are using error feedback (HEC) or error feedforward.

Cheers,
Bob

Hi Bob,

The overall behavior is not the same. Regarding phase margin and reactive loads, error feed forward is much more stable than error feedback. Why? Because error feed forward doesn't rely on a NFB loop with a huge gain.

Cheers, Edmond.
 
ingrast said:



Bob,

I am afraid the casual reader may be led to the conclusion feddback and feedforward error correction schemes are equivalent as much as results (as per simulation) are similar. Sure this is not what you mean.

Rodolfo

PS. By the way, did you notice this post ?


The two techniques are different, but in an apples-to-apples simulation their performance is virtually identical. This was startling even to me.

The key point of being apples-to-apples is that the same compensation roll-off in the error path that is needed to stabilize the HEC is also present in the error path when the error is fed forward.

Commonalities
- both have adjustment that provides an error minima
- both depend on accurate amplitude and phase matching
- both produce the same distortion spectra
- both drove THD-1 from 0.08% down to 0.000064%


Differences
- the feedforward summer is difficult to realize in practice
- the HEC requires frequency compensation

The schematic of my simulation circuit is shown below. C1, R4 and R6 represent the compensation circuit. C2 represents finite bandwidth of the summer. Obviously, in a real circuit, your mileage will vary.


I’m sorry I missed that earlier post. I’ll try to reply to it later in a separate post.

Cheers,
Bob
 

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Edmond Stuart said:


Hi Bob,

The overall behavior is not the same. Regarding phase margin and reactive loads, error feed forward is much more stable than error feedback. Why? Because error feed forward doesn't rely on a NFB loop with a huge gain.

Cheers, Edmond.


I should have said that the error correction performance was virtually the same. You are right - the HEC scheme requires compensation and the feedforward scheme does not. Moreover, stability into arbitrary capacitive loads will of course be different. These are reasonable caveats. My amplifier only required a 0.5 uH and 0.5 ohm output isolation network to achieve unconditional stability. This is certainly not unreasonable.

On the other hand, I dare you to realize in a practical way the output summer needed to do the analogous error correction function with error feedforward.

Cheers,
Bob
 
Bob Cordell said:


.... the same compensation roll-off in the error path that is needed to stabilize the HEC is also present in the error path when the error is fed forward.......

Why? What I am missing here? Unless what you are implying is the error processing must be performed actively (true for proper "cancellation") what in turn implies at least one pole.



......
Differences
- the feedforward summer is difficult to realize in practice
- the HEC requires frequency compensation

Neat

Now, this feedforward thing is intriguing. If one could process the error (orders of magnitude larger bandwidth than working bandwidth) and inject passively regardeless of load magnitude and phase angle variations .... Of course for this to be devoid of stability issues, the error pick up point must be as in your test circuit BEFORE the output summing node, otherwise it is feedback bussiness as usual.

Rodolfo
 
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Bob Cordell said:
[snip]On the other hand, I dare you to realize in a practical way the output summer needed to do the analogous error correction function with error feedforward.

Cheers,
Bob


'Practical" is probably a matter of perspective, but Stochino tried his hand at this.

Jan Didden
 

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janneman said:
In theory, you actually lose the distortion null, but in practise the difference may not be that large.

In theory you don't lose the null. I'll put the results of the math at the end.

I guess the attached is the concept of what you propose. If you now work out Vout/Vin you get:

Vout/Vin = N/(1-P.Q+N.Q), with N the non-lin gain block you want to compensate, P the attenuator and Q the compensation gain.
It's obvious that N drops out only if Q=1 AND Q.P=1, so both the attenuator and the compensation gain should always be 1 for distortion cancellation.

There's something missing from your block diagram. At the output node, the block diagram should show a summer adding in the error like so:

Vout = N * Vn + err

Then, the goal is to express Vout as a function of Vin, N, P, Q and err, and find conditions such that the term involving err drops out. I did this with a block diagram similar to yours, except that the plus and minus signs were reversed in the summer on the right side, and the summer on the left had a minus term associated with Q. I got this result:

Vout = [1 / (1 + NQ - PQ)] * [N * Vin + (1 - PQ) * err]

So when PQ=1, err goes away. and Vout/Vin = P (=1/Q)

Last year when I was playing around with this in sim, I had the very same problem with losing the distortion null when optimizing EC dynamic range. After playing around with the block diagram equations as above and implementing the diff amp gain fix, the null (using idealized controlled sources for the summers) came back and the distortion was below the ~-180 dB residual of LTSpice.

Edit: In your equation above, it's only necessary that PQ=1. For this condition, Vout/Vin = N / NQ = 1/Q = P. It's not necessary that Q=1.
 
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andy_c said:
[snip]
Edit: In your equation above, it's only necessary that PQ=1. For this condition, Vout/Vin = N / NQ = 1/Q = P. It's not necessary that Q=1.


Indeed, my equation was correct, but I interpreted it incorrect. That then means that the final gain of the circuit becomes 1/Q or, in the this example, about 0.95, correct? With the 1.05 X gain correction?

Jan Didden
 
janneman said:
Indeed, my equation was correct, but I interpreted it incorrect. That then means that the final gain of the circuit becomes 1/Q or, in the this example, about 0.95, correct? With the 1.05 X gain correction?

Sounds right! :) Or another way of looking at it is that the final gain is the same as the voltage divider ratio. And the voltage divider makes a great place for the distortion trim pot.

I think you could make a good case that I'm overemphasizing the importance of maximizing the dynamic range of the EC. But the idea I had for my design was, in simulation, to minimize the distortion of the output stage itself under very high current conditions (say, 100A peak). So it was just a way to try to make the EC as robust as possible.
 
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andy_c said:


Sounds right! :) Or another way of looking at it is that the final gain is the same as the voltage divider ratio. And the voltage divider makes a great place for the distortion trim pot.

I think you could make a good case that I'm overemphasizing the importance of maximizing the dynamic range of the EC. But the idea I had for my design was, in simulation, to minimize the distortion of the output stage itself under very high current conditions (say, 100A peak). So it was just a way to try to make the EC as robust as possible.


No I think your emphasis is right to the point. In my implementation I use a current conveyor as the ec element, and that CC runs open loop. I don't use additional nfb around the amp. The final result depends very much on the linearity of that open loop CC. Optimizing things like you did with the 0.95 attenuator decreases the signal levels in the ec circuit and improves overall results.

On a side note, I find it counter-intuitive that the final gain with the 1.05 gain correction comes out to 0.95 . Or maybe my intuition isn't what it used to be ;)

Jan Didden
 
janneman said:
On a side note, I find it counter-intuitive that the final gain with the 1.05 gain correction comes out to 0.95 . Or maybe my intuition isn't what it used to be ;)

I think of it this way. If the voltage divider ratio is the exact same as the linear gain of the output stage, then for a distortionless output stage the error signal will be exactly zero. If the error signal is exactly zero, the EC isn't doing anything at all, so the gain with EC will be the same as the gain without EC.

Of course, if the voltage divider ratio does not equal the linear gain of the output stage, then my intuition fails too. This is where my time-tested approach of using math as a crutch comes in :).
 
janneman said:
'Practical" is probably a matter of perspective, but Stochino tried his hand at this.
Jan Didden

Hi Jan,

I too was thinking about his design. It was most interesting as far as I can remember. Regrettably, I failed to find it back in my large pile of Electronics World magazines. According to D. Self's website it was published in Oct. 1994, p. 818. Does anyone have a pdf copy? TIA.

Cheers, Edmond.