The LX75 versions (latest is 2.1) have more and longer FIR filters in the interpolation chain, but they also need more and longer filters because of a stupid choice of the quantizer sample rates in the PWM modes.
The LX45 version (version 3) has a shorter FIR filter and one less interpolation stage, but it also has a better choice of the quantizer sample rates in the PWM modes.
In either case, passband ripple is dominated by the SRC4392's interpolation chain (its decimation chain is not used). I have workarounds in place for its intersample issues and transition band that extends above Nyquist, but not for the ripples.
See the attachments for details.
The LX45 version (version 3) has a shorter FIR filter and one less interpolation stage, but it also has a better choice of the quantizer sample rates in the PWM modes.
In either case, passband ripple is dominated by the SRC4392's interpolation chain (its decimation chain is not used). I have workarounds in place for its intersample issues and transition band that extends above Nyquist, but not for the ripples.
See the attachments for details.
Attachments
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The FIR filters inside the FPGA have no rounding of intermediate results, like hardware FIR filters often have. The filter calculations are done in full precision and when wordlength reduction is needed, it is done by dithered rounding stages between the filters. No idea what exactly is done inside the SRC4392, though. (This is additional information, not a reply to post #103.)
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Yes, I think so. It is more elegant anyway to have non-stupid quantizer sample rates. The last time I looked, both the TE0630 LX45 and the TE0630 LX75 were out of stock at Trenz Electronic.
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The honest answer is I don't know.
clock5 and clockn5 are relatively short compared to sdclock (roughly about 8 cm, about 9.5 cm and about 25 cm). The rise and fall time of the SN74LVC2G86 that drives them is of the order of 2 ns at 5 V. I've probably guesstimated that the lines are short enough for the signal to bounce back and forth a couple of times within the rise or fall time, and decided to treat them as nodes rather than transmission lines. KiCad predicts a speed of propagation of 0.17726 m/ns (*), so that's about two times from one end to the other and back within a transition time.
However, that doesn't take into account the relatively large capacitive load on these lines. If I counted correctly, clock5 drives 7 inputs and clockn5 drives 20 inputs. The inputs are usually specified to have a 3 pF typical input capacitance, so that's 21 pF and 60 pF on top of the line capacitance. Pretending the extra capacitance is spread evenly over the length of the line, that effectively reduces the characteristic impedance and the speed of propagation to about 37 ohm and 0.0813 m/ns for clock5 and about 25.5 ohm and 0.05596 m/ns for clockn5.
The output resistance of the SN74LVC2G86 that drives clock5 and clockn5 is of the order of 10 ohm to 15 ohm, so all in all, the waveforms might improve a bit with 15 ohm series resistors between the SN74LVC2G86 and clock5/clockn5. That said, I haven't noticed any issues related to reflections on these clock lines, but I also haven't specifically looked for them.
(*): When you enter a microstrip with 0.25 mm track width and a dielectric layer of 0.36 mm, epsilon_R = 4.35 in the KiCad calculator, it says the characteristic impedance is 80.6924 ohm and the epsilon_eff is 2.86031. From that you can calculate a speed of propagation of 177 261 390.1 m/s, a capacitance per unit length of 69.9122399 pF/m and an inductance per unit length of 455.2170101 nH/m.
clock5 and clockn5 are relatively short compared to sdclock (roughly about 8 cm, about 9.5 cm and about 25 cm). The rise and fall time of the SN74LVC2G86 that drives them is of the order of 2 ns at 5 V. I've probably guesstimated that the lines are short enough for the signal to bounce back and forth a couple of times within the rise or fall time, and decided to treat them as nodes rather than transmission lines. KiCad predicts a speed of propagation of 0.17726 m/ns (*), so that's about two times from one end to the other and back within a transition time.
However, that doesn't take into account the relatively large capacitive load on these lines. If I counted correctly, clock5 drives 7 inputs and clockn5 drives 20 inputs. The inputs are usually specified to have a 3 pF typical input capacitance, so that's 21 pF and 60 pF on top of the line capacitance. Pretending the extra capacitance is spread evenly over the length of the line, that effectively reduces the characteristic impedance and the speed of propagation to about 37 ohm and 0.0813 m/ns for clock5 and about 25.5 ohm and 0.05596 m/ns for clockn5.
The output resistance of the SN74LVC2G86 that drives clock5 and clockn5 is of the order of 10 ohm to 15 ohm, so all in all, the waveforms might improve a bit with 15 ohm series resistors between the SN74LVC2G86 and clock5/clockn5. That said, I haven't noticed any issues related to reflections on these clock lines, but I also haven't specifically looked for them.
(*): When you enter a microstrip with 0.25 mm track width and a dielectric layer of 0.36 mm, epsilon_R = 4.35 in the KiCad calculator, it says the characteristic impedance is 80.6924 ohm and the epsilon_eff is 2.86031. From that you can calculate a speed of propagation of 177 261 390.1 m/s, a capacitance per unit length of 69.9122399 pF/m and an inductance per unit length of 455.2170101 nH/m.
Actually I did find closed-form expressions for step E, see the attachment - even though Hans doesn't require them, it seemed a good idea to write them down in a form that is still readable a few years from now. I haven't checked yet whether the equations in the attachment actually give the correct values and I don't know anymore how I sized the output stage.
Thx.
In the meantime I've ordered the LX45 from Trenz.
Expected delivery is 22-10, so I have all the time to prepare the rest.
What will be needed to load your files into the FPGA, hardware and software?
Hans
A JTAG interface cable such as the Digilent JTAG-HS2 and the free (webpack) version of the Xilinx ISE software, or at least the part that programs .mcs files into the module. I used ISE 14.6, but the last version, ISE 14.7, should also work.
By the way, my calculations are correct, see the attachment. At least they produce the same results as before and I've checked those with a pole-zero extraction program.
By the way, my calculations are correct, see the attachment. At least they produce the same results as before and I've checked those with a pole-zero extraction program.
Marcel,
I've also ordered the PCB's, 5 in total, the minimum production amount.
So when somebody is interested in PCBs, he should let me know.
Is there a BOM ?
All straightforward components I can find on the circuit diagram, but there are probably a number of specials that are not that straightforward, like connectors.
It would be helpful if you could point me in the direction.
Last point and of lesser importance is the noise produced by the 7th order LPF.
With a max diff output of 1.96Vrms and with 16uV A-weighted diff noise from 20Hz to 20Khz, S/N of this LPF alone is just slightly below -100dB(A)
The completed Dac shows a S/N, as you specified, at slightly above -100dB(A), so there is still something to be gained here, although may be academical.
Hans
I've also ordered the PCB's, 5 in total, the minimum production amount.
So when somebody is interested in PCBs, he should let me know.
Is there a BOM ?
All straightforward components I can find on the circuit diagram, but there are probably a number of specials that are not that straightforward, like connectors.
It would be helpful if you could point me in the direction.
Last point and of lesser importance is the noise produced by the 7th order LPF.
With a max diff output of 1.96Vrms and with 16uV A-weighted diff noise from 20Hz to 20Khz, S/N of this LPF alone is just slightly below -100dB(A)
The completed Dac shows a S/N, as you specified, at slightly above -100dB(A), so there is still something to be gained here, although may be academical.
Hans
I usually put a .csv file generated by KiCad in the .zip with the KiCad data, but apparently I forgot to do so. Anyway, see the attachment (renamed to .txt to pass the forum software).
Mind you, I've cheated a bit with some footprints. I sometimes use 3 mm by 3 mm TSSOP-8 footprints with 0.65 mm pitch from a standard KiCad library, while the actual package type is SSOP-8, also known as SM8 or SM-8. They are compatible, but it is confusing. This applies to U14, U18 and U25. The TI package code in the type number is DCT.
You need two special connectors from Hirose for the FPGA module, hard to solder 80-pin 0.5 mm pitch connectors. Trenz Electronic normally has them in stock:
B2B Stecker Hirose fur TE0300/TE0630 Industrie Mikromodul | Trenz Electronic GmbH Online Shop (DE)
Digi-Key also sells them, as far as I recall. Trenz also has the JTAG interface for programming, although they have only one in stock at the moment:
JTAG HS2 Programmierkabel | Trenz Electronic GmbH Online Shop (DE)
It can also be found elsewhere and there are probably cheaper alternatives, but this is the only model I ever used.
Regarding the filter, at least it doesn't dominate the noise now. I guess its noise can still be reduced a bit by reducing the impedance levels, but when you do that in the first stage, it will aggravate the effect of differences in high and low output resistance. There must be an optimum somewhere, but I don't know where.
Mind you, I've cheated a bit with some footprints. I sometimes use 3 mm by 3 mm TSSOP-8 footprints with 0.65 mm pitch from a standard KiCad library, while the actual package type is SSOP-8, also known as SM8 or SM-8. They are compatible, but it is confusing. This applies to U14, U18 and U25. The TI package code in the type number is DCT.
You need two special connectors from Hirose for the FPGA module, hard to solder 80-pin 0.5 mm pitch connectors. Trenz Electronic normally has them in stock:
B2B Stecker Hirose fur TE0300/TE0630 Industrie Mikromodul | Trenz Electronic GmbH Online Shop (DE)
Digi-Key also sells them, as far as I recall. Trenz also has the JTAG interface for programming, although they have only one in stock at the moment:
JTAG HS2 Programmierkabel | Trenz Electronic GmbH Online Shop (DE)
It can also be found elsewhere and there are probably cheaper alternatives, but this is the only model I ever used.
Regarding the filter, at least it doesn't dominate the noise now. I guess its noise can still be reduced a bit by reducing the impedance levels, but when you do that in the first stage, it will aggravate the effect of differences in high and low output resistance. There must be an optimum somewhere, but I don't know where.
Marcel,
Thx for all info you provided, also for the filter calculations.
What is puzzling me is why you have chosen for a 7th order LPF.
The SDM will produce all sorts of output up to 27Mhz including lots of HF noise, but do we really need such a steep filter that’s already 140dB down at 1Mhz ?
The other question I would like to ask, did you handsolder the more complex components or did you use a hot air gun ?
Hans
Thx for all info you provided, also for the filter calculations.
What is puzzling me is why you have chosen for a 7th order LPF.
The SDM will produce all sorts of output up to 27Mhz including lots of HF noise, but do we really need such a steep filter that’s already 140dB down at 1Mhz ?
The other question I would like to ask, did you handsolder the more complex components or did you use a hot air gun ?
Hans
I handsoldered everything.
See posts #16...#22 for your other question. I'dd like to add that I chose an odd order so I could put a little passive filtering in front of the first op-amp. The sigma-delta output quantization noise density will increase steeply above the highest notch, which if I remember well is just above 40 kHz (somewhere in the middle of the feline auditory range). It then levels off at a few hundred kHz, depending on which mode you use.
See posts #16...#22 for your other question. I'dd like to add that I chose an odd order so I could put a little passive filtering in front of the first op-amp. The sigma-delta output quantization noise density will increase steeply above the highest notch, which if I remember well is just above 40 kHz (somewhere in the middle of the feline auditory range). It then levels off at a few hundred kHz, depending on which mode you use.
360 um prepreg thickness? If not, a few resistors may have to be adjusted.